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Searched refs:val6 (Results 1 – 25 of 178) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/SystemZ/
Dscalar-cmp-cmp-log-sel.ll6 i8 %val5, i8 %val6) {
10 %sel = select i1 %and, i8 %val5, i8 %val6
17 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i8 %val5, i8 %val6
21 i16 %val5, i16 %val6) {
25 %sel = select i1 %and, i16 %val5, i16 %val6
32 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i16 %val5, i16 %val6
36 i32 %val5, i32 %val6) {
40 %sel = select i1 %and, i32 %val5, i32 %val6
47 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i32 %val5, i32 %val6
51 i64 %val5, i64 %val6) {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-cmp-cmp-logic-select.ll8 …0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
19 %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
23 …<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
35 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
39 …i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
52 %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
56 …> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
75 %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
79 …x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4, <32 x i8> %val5, <32 x i8> %val6) {
98 %sel = select <32 x i1> %and, <32 x i8> %val5, <32 x i8> %val6
[all …]
Dspill-01.ll53 %val6 = load i32, i32 *%ptr6
63 store i32 %val6, i32 *%ptr6
91 %val6 = load i32, i32 *%ptr6
103 store i32 %val6, i32 *%ptr6
133 %val6 = load i64, i64 *%ptr6
145 store i64 %val6, i64 *%ptr6
179 %val6 = load float, float *%ptr6
192 store float %val6, float *%ptr6
223 %val6 = load double, double *%ptr6
236 store double %val6, double *%ptr6
[all …]
Dint-add-12.ll142 %val6 = load volatile i64, i64 *%ptr
163 %add6 = add i64 %val6, 127
182 %new6 = phi i64 [ %val6, %entry ], [ %add6, %add ]
225 %val6 = load volatile i64, i64 *%ptr
246 %add6 = add i64 %val6, -128
265 %new6 = phi i64 [ %val6, %entry ], [ %add6, %add ]
Dint-add-11.ll143 %val6 = load volatile i32, i32 *%ptr
164 %add6 = add i32 %val6, 127
183 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
226 %val6 = load volatile i32, i32 *%ptr
247 %add6 = add i32 %val6, -128
266 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
/external/u-boot/board/toradex/colibri_imx6/
Ddo_fuse.c17 unsigned val, val6; in mfgr_fuse() local
21 fuse_sense(0, 6, &val6); in mfgr_fuse()
22 printf("Fuse 0, 6: %8x\n", val6); in mfgr_fuse()
27 if (val6 & 0x10) { in mfgr_fuse()
/external/u-boot/board/toradex/apalis_imx6/
Ddo_fuse.c17 unsigned val, val6; in mfgr_fuse() local
21 fuse_sense(0, 6, &val6); in mfgr_fuse()
22 printf("Fuse 0, 6: %8x\n", val6); in mfgr_fuse()
27 if (val6 & 0x10) { in mfgr_fuse()
/external/llvm/test/CodeGen/SystemZ/
Dspill-01.ll53 %val6 = load i32 , i32 *%ptr6
63 store i32 %val6, i32 *%ptr6
91 %val6 = load i32 , i32 *%ptr6
103 store i32 %val6, i32 *%ptr6
133 %val6 = load i64 , i64 *%ptr6
145 store i64 %val6, i64 *%ptr6
179 %val6 = load float , float *%ptr6
192 store float %val6, float *%ptr6
223 %val6 = load double , double *%ptr6
236 store double %val6, double *%ptr6
[all …]
Dint-add-11.ll143 %val6 = load volatile i32 , i32 *%ptr
164 %add6 = add i32 %val6, 127
183 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
226 %val6 = load volatile i32 , i32 *%ptr
247 %add6 = add i32 %val6, -128
266 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dfloatdp_2source.ll25 %val6 = fmul float %val1, %val2
26 %val7 = fsub float -0.0, %val6
53 %val6 = fmul double %val1, %val2
54 %val7 = fsub double -0.0, %val6
Daddsub-shifted.ll48 %val6 = add i64 %shift6, %lhs64
49 store volatile i64 %val6, i64* @var64
110 %val6 = add i64 %shift6, %lhs64
111 store volatile i64 %val6, i64* @var64
169 %val6 = add i64 %shift6, %lhs64
170 store volatile i64 %val6, i64* @var64
289 %val6 = sub i64 0, %shift6
290 %tst6 = icmp ne i64 %lhs64, %val6
Dregress-w29-reserved-with-fp.ll15 %val6 = load volatile i32, i32* @var
30 store volatile i32 %val6, i32* @var
/external/llvm/test/CodeGen/AArch64/
Dfloatdp_2source.ll25 %val6 = fmul float %val1, %val2
26 %val7 = fsub float -0.0, %val6
53 %val6 = fmul double %val1, %val2
54 %val7 = fsub double -0.0, %val6
Daddsub-shifted.ll48 %val6 = add i64 %shift6, %lhs64
49 store volatile i64 %val6, i64* @var64
110 %val6 = add i64 %shift6, %lhs64
111 store volatile i64 %val6, i64* @var64
169 %val6 = add i64 %shift6, %lhs64
170 store volatile i64 %val6, i64* @var64
289 %val6 = sub i64 0, %shift6
290 %tst6 = icmp ne i64 %lhs64, %val6
Dregress-w29-reserved-with-fp.ll15 %val6 = load volatile i32, i32* @var
30 store volatile i32 %val6, i32* @var
/external/swiftshader/third_party/LLVM/test/Transforms/SimplifyLibCalls/
DToAscii.ll13 %val6 = call i32 @toascii( i32 256 ) ; <i32> [#uses=1]
16 %rslt3 = add i32 %val5, %val6 ; <i32> [#uses=1]
DFFS.ll21 %val6 = call i32 @ffsll( i64 1152921504606846976 ) ; <i32> [#uses=1]
24 %rslt3 = add i32 %val5, %val6 ; <i32> [#uses=1]
/external/llvm/test/CodeGen/ARM/
Dinlineasm-64bit.ll13 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6…
37 …"r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
39 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
40 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
Dgpr-paired-spill-thumbinst.ll14 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
27 store volatile i64 %val6, i64* %addr
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dinlineasm-64bit.ll13 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6…
37 …"r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
39 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
40 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
Dgpr-paired-spill-thumbinst.ll14 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
27 store volatile i64 %val6, i64* %addr
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/
Dselect-cc.ll69 %val6 = select i1 %tst3, i32 %val4, i32 %val5
72 %tst4 = icmp uge i32 %val6, %val7
73 %val8 = select i1 %tst4, i32 %val6, i32 %val7
/external/u-boot/board/sks-kinkel/sksimx6/
Dsksimx6.c379 u32 val5, val6; in check_bootcfg() local
382 fuse_sense(0, 6, &val6); in check_bootcfg()
384 if (val6 & 0x10) { in check_bootcfg()
/external/llvm/test/CodeGen/AMDGPU/
Dds_read2_offset_order.ll41 %val6 = load float, float addrspace(3)* %ptr6
42 %add6 = fadd float %add5, %val6
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dds_read2_offset_order.ll39 %val6 = load float, float addrspace(3)* %ptr6
40 %add6 = fadd float %add5, %val6

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