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Searched refs:vbsl (Results 1 – 25 of 67) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvbsl.ll7 ;CHECK: vbsl
20 ;CHECK: vbsl
33 ;CHECK: vbsl
46 ;CHECK: vbsl
59 ;CHECK: vbsl
72 ;CHECK: vbsl
85 ;CHECK: vbsl
98 ;CHECK: vbsl
111 ; CHECK: vbsl
112 …%vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounw…
[all …]
Dvselect_imax.ll69 ; CHECK: vbsl
70 ; CHECK: vbsl
85 ; CHECK: vbsl
86 ; CHECK: vbsl
87 ; CHECK: vbsl
88 ; CHECK: vbsl
103 ; CHECK: vbsl
104 ; CHECK: vbsl
105 ; CHECK: vbsl
106 ; CHECK: vbsl
[all …]
Dvbsl-constant.ll7 ;CHECK: vbsl
21 ;CHECK: vbsl
35 ;CHECK: vbsl
50 ;CHECK: vbsl
64 ;CHECK: vbsl
78 ;CHECK: vbsl
92 ;CHECK: vbsl
107 ;CHECK: vbsl
Dfcopysign.ll13 ; HARD: vbsl [[REG1]], d
27 ; HARD: vbsl [[REG2]], d1, d0
37 ; SOFT: vbsl [[REG3]],
50 ; SOFT: vbsl [[REG6]], [[REG7]],
/external/llvm/test/CodeGen/ARM/
Dvbsl.ll7 ;CHECK: vbsl
20 ;CHECK: vbsl
33 ;CHECK: vbsl
46 ;CHECK: vbsl
59 ;CHECK: vbsl
72 ;CHECK: vbsl
85 ;CHECK: vbsl
98 ;CHECK: vbsl
111 ; CHECK: vbsl
112 …%vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounw…
[all …]
Dvselect_imax.ll69 ; CHECK: vbsl
70 ; CHECK: vbsl
85 ; CHECK: vbsl
86 ; CHECK: vbsl
87 ; CHECK: vbsl
88 ; CHECK: vbsl
103 ; CHECK: vbsl
104 ; CHECK: vbsl
105 ; CHECK: vbsl
106 ; CHECK: vbsl
[all …]
Dvbsl-constant.ll7 ;CHECK: vbsl
21 ;CHECK: vbsl
35 ;CHECK: vbsl
50 ;CHECK: vbsl
64 ;CHECK: vbsl
78 ;CHECK: vbsl
92 ;CHECK: vbsl
107 ;CHECK: vbsl
Dfcopysign.ll13 ; HARD: vbsl [[REG1]], d
27 ; HARD: vbsl [[REG2]], d1, d0
37 ; SOFT: vbsl [[REG3]],
50 ; SOFT: vbsl [[REG6]], [[REG7]],
Dvuzp.ll309 ; CHECK: vbsl
317 ; to perform the vuzp and get the vbsl mask.
323 ; CHECK: vbsl
338 ; CHECK: vbsl
351 ; CHECK: vbsl
365 ; CHECK: vbsl
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_vert.s223 vbsl d18, d24, d16 @only select row values from q12(predpixel)
224 vbsl d10, d25, d16
239 vbsl d8, d24, d16 define
240 vbsl d6, d25, d16 define
264 vbsl d18, d24, d16 @only select row values from q12(predpixel)
265 vbsl d10, d25, d16
277 vbsl d8, d24, d16 define
278 vbsl d6, d25, d16 define
294 vbsl d18, d24, d16 @only select row values from q12(predpixel)
295 vbsl d10, d25, d16
[all …]
Dihevc_intra_pred_luma_dc.s477 vbsl d19, d15, d2 @first row with dst[0]
486 vbsl d20, d3, d16 @row 1 (prol)
491 vbsl d21, d3, d16 @row 2 (prol)
498 vbsl d20, d3, d16 @row 3 (prol)
Dihevc_deblk_luma_vert.s523 vbsl d3,d30,d16 define
533 vbsl d16,d2,d22
578 vbsl d5,d30,d3 define
589 vbsl d0,d4,d23 define
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Dselect-vec.ll33 ; ASM-NEXT: vbsl.i32 [[M]], {{.*}}
39 ; IASM-NOT: vbsl
54 ; ASM-NEXT: vbsl.i32 [[M]], {{.*}}
60 ; IASM-NOT: vbsl
75 ; ASM-NEXT: vbsl.i16 [[M]], {{.*}}
81 ; IASM-NOT: vbsl
97 ; ASM-NEXT: vbsl.i8 [[M]], {{.*}}
103 ; IASM-NOT: vbsl
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dfcopysign.ll13 ; HARD: vbsl [[REG1]], d
27 ; HARD: vbsl [[REG2]], d1, d0
37 ; SOFT: vbsl [[REG3]],
48 ; This S-reg must be the first sub-reg of the last D-reg on vbsl.
52 ; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}}
66 ; SOFT: vbsl [[REG6]], [[REG7]],
Dvbsl.ll5 ;CHECK: vbsl
18 ;CHECK: vbsl
31 ;CHECK: vbsl
44 ;CHECK: vbsl
57 ;CHECK: vbsl
70 ;CHECK: vbsl
83 ;CHECK: vbsl
96 ;CHECK: vbsl
Dvbsl-constant.ll7 ;CHECK: vbsl
21 ;CHECK: vbsl
35 ;CHECK: vbsl
50 ;CHECK: vbsl
64 ;CHECK: vbsl
78 ;CHECK: vbsl
92 ;CHECK: vbsl
107 ;CHECK: vbsl
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-bitwise-encoding.s51 vbsl d18, d17, d16
52 vbsl q8, q10, q9
54 @ CHECK: vbsl d18, d17, d16 @ encoding: [0x51,0xff,0xb0,0x21]
55 @ CHECK: vbsl q8, q10, q9 @ encoding: [0x54,0xff,0xf2,0x01]
Dneon-bitwise-encoding.s51 vbsl d18, d17, d16
52 vbsl q8, q10, q9
54 @ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3]
55 @ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneont2-bitwise-encoding.s51 vbsl d18, d17, d16
52 vbsl q8, q10, q9
54 @ CHECK: vbsl d18, d17, d16 @ encoding: [0x51,0xff,0xb0,0x21]
55 @ CHECK: vbsl q8, q10, q9 @ encoding: [0x54,0xff,0xf2,0x01]
Dneon-bitwise-encoding.s102 vbsl d18, d17, d16
103 vbsl q8, q10, q9
105 @ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3]
106 @ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3]
/external/llvm/test/MC/ARM/
Dneont2-bitwise-encoding.s51 vbsl d18, d17, d16
52 vbsl q8, q10, q9
54 @ CHECK: vbsl d18, d17, d16 @ encoding: [0x51,0xff,0xb0,0x21]
55 @ CHECK: vbsl q8, q10, q9 @ encoding: [0x54,0xff,0xf2,0x01]
Dneon-bitwise-encoding.s102 vbsl d18, d17, d16
103 vbsl q8, q10, q9
105 @ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3]
106 @ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3]
/external/capstone/suite/MC/ARM/
Dneont2-bitwise-encoding.s.cs14 0x51,0xff,0xb0,0x21 = vbsl d18, d17, d16
15 0x54,0xff,0xf2,0x01 = vbsl q8, q10, q9
Dneon-bitwise-encoding.s.cs21 0xb0,0x21,0x51,0xf3 = vbsl d18, d17, d16
22 0xf2,0x01,0x54,0xf3 = vbsl q8, q10, q9
/external/libavc/common/arm/
Dih264_resi_trans_quant_a9.s218 vbsl.s16 q2, q1, q15 @Restore sign of row 1 and 2
219 vbsl.s16 q3, q4, q0 @Restore sign of row 3 and 4
413 vbsl.s16 q2, q1, q15 @Restore sign of row 1 and 2
414 vbsl.s16 q3, q4, q0 @Restore sign of row 3 and 4
554 vbsl.s16 q3, q13, q11
555 vbsl.s16 q4, q14, q12
669 vbsl.s16 q4, q6, q5 @*sign

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