| /external/llvm/test/MC/Hexagon/ |
| D | v60-vcmp.s | 5 #CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) }
6 q2|=vcmp.eq(v17.b,v1.b)
8 #CHECK: 1c84fb2a { q2 &= vcmp.gt(v27.uw{{ *}},{{ *}}v4.uw) }
9 q2&=vcmp.gt(v27.uw,v4.uw)
11 #CHECK: 1c8cf826 { q2 &= vcmp.gt(v24.uh{{ *}},{{ *}}v12.uh) }
12 q2&=vcmp.gt(v24.uh,v12.uh)
14 #CHECK: 1c80e720 { q0 &= vcmp.gt(v7.ub{{ *}},{{ *}}v0.ub) }
15 q0&=vcmp.gt(v7.ub,v0.ub)
17 #CHECK: 1c9aed1a { q2 &= vcmp.gt(v13.w{{ *}},{{ *}}v26.w) }
18 q2&=vcmp.gt(v13.w,v26.w)
[all …]
|
| D | v60-misc.s | 26 # CHECK: 1f90cf00 { q0 = vcmp.eq(v15.b,v16.b) }
27 q0 = vcmp.eq(v15.ub, v16.ub)
29 # CHECK: 1c92f101 { q1 &= vcmp.eq(v17.b,v18.b) }
30 q1 &= vcmp.eq(v17.ub, v18.ub)
32 # CHECK: 1c94f342 { q2 |= vcmp.eq(v19.b,v20.b) }
33 q2 |= vcmp.eq(v19.ub, v20.ub)
35 # CHECK: 1c96f583 { q3 ^= vcmp.eq(v21.b,v22.b) }
36 q3 ^= vcmp.eq(v21.ub, v22.ub)
38 # CHECK: 1f81c004 { q0 = vcmp.eq(v0.h,v1.h) }
39 q0 = vcmp.eq(v0.uh, v1.uh)
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/ |
| D | v60-vcmp.s | 5 #CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) }
6 q2|=vcmp.eq(v17.b,v1.b)
8 #CHECK: 1c84fb2a { q2 &= vcmp.gt(v27.uw{{ *}},{{ *}}v4.uw) }
9 q2&=vcmp.gt(v27.uw,v4.uw)
11 #CHECK: 1c8cf826 { q2 &= vcmp.gt(v24.uh{{ *}},{{ *}}v12.uh) }
12 q2&=vcmp.gt(v24.uh,v12.uh)
14 #CHECK: 1c80e720 { q0 &= vcmp.gt(v7.ub{{ *}},{{ *}}v0.ub) }
15 q0&=vcmp.gt(v7.ub,v0.ub)
17 #CHECK: 1c9aed1a { q2 &= vcmp.gt(v13.w{{ *}},{{ *}}v26.w) }
18 q2&=vcmp.gt(v13.w,v26.w)
[all …]
|
| D | v60-misc.s | 26 # CHECK: 1f90cf00 { q0 = vcmp.eq(v15.b,v16.b) }
27 q0 = vcmp.eq(v15.ub, v16.ub)
29 # CHECK: 1c92f101 { q1 &= vcmp.eq(v17.b,v18.b) }
30 q1 &= vcmp.eq(v17.ub, v18.ub)
32 # CHECK: 1c94f342 { q2 |= vcmp.eq(v19.b,v20.b) }
33 q2 |= vcmp.eq(v19.ub, v20.ub)
35 # CHECK: 1c96f583 { q3 ^= vcmp.eq(v21.b,v22.b) }
36 q3 ^= vcmp.eq(v21.ub, v22.ub)
38 # CHECK: 1f81c004 { q0 = vcmp.eq(v0.h,v1.h) }
39 q0 = vcmp.eq(v0.uh, v1.uh)
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/ |
| D | vector-compare-128b.ll | 6 ; CHECK: q[[Q000:[0-3]]] = vcmp.eq(v0.b,v1.b)
15 ; CHECK: q[[Q010:[0-3]]] = vcmp.eq(v0.b,v1.b)
24 ; CHECK: q[[Q020:[0-3]]] = vcmp.gt(v1.b,v0.b)
33 ; CHECK: q[[Q030:[0-3]]] = vcmp.gt(v0.b,v1.b)
42 ; CHECK: q[[Q040:[0-3]]] = vcmp.gt(v0.b,v1.b)
51 ; CHECK: q[[Q050:[0-3]]] = vcmp.gt(v1.b,v0.b)
60 ; CHECK: q[[Q060:[0-3]]] = vcmp.gt(v1.ub,v0.ub)
69 ; CHECK: q[[Q070:[0-3]]] = vcmp.gt(v0.ub,v1.ub)
78 ; CHECK: q[[Q080:[0-3]]] = vcmp.gt(v0.ub,v1.ub)
87 ; CHECK: q[[Q090:[0-3]]] = vcmp.gt(v1.ub,v0.ub)
[all …]
|
| D | vector-compare-64b.ll | 6 ; CHECK: q[[Q000:[0-3]]] = vcmp.eq(v0.b,v1.b)
15 ; CHECK: q[[Q010:[0-3]]] = vcmp.eq(v0.b,v1.b)
24 ; CHECK: q[[Q020:[0-3]]] = vcmp.gt(v1.b,v0.b)
33 ; CHECK: q[[Q030:[0-3]]] = vcmp.gt(v0.b,v1.b)
42 ; CHECK: q[[Q040:[0-3]]] = vcmp.gt(v0.b,v1.b)
51 ; CHECK: q[[Q050:[0-3]]] = vcmp.gt(v1.b,v0.b)
60 ; CHECK: q[[Q060:[0-3]]] = vcmp.gt(v1.ub,v0.ub)
69 ; CHECK: q[[Q070:[0-3]]] = vcmp.gt(v0.ub,v1.ub)
78 ; CHECK: q[[Q080:[0-3]]] = vcmp.gt(v0.ub,v1.ub)
87 ; CHECK: q[[Q090:[0-3]]] = vcmp.gt(v1.ub,v0.ub)
[all …]
|
| /external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
| D | vcmp.ll | 1 ; Show that we know how to translate vcmp.
35 ; ASM: vcmp.f32 s0, s1
37 ; IASM-NOT: vcmp
54 ; ASM: vcmp.f32 s0, #0.0
56 ; IASM-NOT: vcmp
73 ; ASM: vcmp.f64 d0, d1
75 ; IASM-NOT: vcmp
92 ; ASM: vcmp.f64 d0, #0.0
94 ; IASM-NOT: vcmp
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrAlias.td | 512 // maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
513 def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
517 // maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
518 def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
522 // maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
523 def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
527 // maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
528 def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
532 // maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
533 def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
[all …]
|
| D | HexagonInstrInfoV60.td | 1477 T_HVX_vcmp <"$dst &= vcmp.eq($src1.b,$src2.b)">, V6_veqb_and_enc;
1479 T_HVX_vcmp <"$dst &= vcmp.eq($src1.h,$src2.h)">, V6_veqh_and_enc;
1481 T_HVX_vcmp <"$dst &= vcmp.eq($src1.w,$src2.w)">, V6_veqw_and_enc;
1483 T_HVX_vcmp <"$dst &= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_and_enc;
1485 T_HVX_vcmp <"$dst &= vcmp.gt($src1.h,$src2.h)">, V6_vgth_and_enc;
1487 T_HVX_vcmp <"$dst &= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_and_enc;
1489 T_HVX_vcmp <"$dst &= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_and_enc;
1491 T_HVX_vcmp <"$dst &= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_and_enc;
1493 T_HVX_vcmp <"$dst &= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_and_enc;
1495 T_HVX_vcmp <"$dst |= vcmp.eq($src1.b,$src2.b)">, V6_veqb_or_enc;
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | intrinsics-v60-vcmp.ll | 6 ; CHECK: q{{[0-9]}} &= vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
17 ; CHECK: q{{[0-9]}} &= vcmp.eq(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
28 ; CHECK: q{{[0-9]}} &= vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
39 ; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
50 ; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
61 ; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
72 ; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)
83 ; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)
94 ; CHECK: q{{[0-9]}} &= vcmp.gt(v{{[0-9]+}}.uw,v{{[0-9]+}}.uw)
105 ; CHECK: q{{[0-9]}} |= vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
[all …]
|
| D | swp-prolog-phi.ll | 8 ; CHECK: vcmp.gt([[VREG:(v[0-9]+)]].uh,v{{[0-9]+}}.uh)
9 ; CHECK-NOT: vcmp.gt([[VREG]].uh,v{{[0-9]+}}.uh)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | vminmaxnm.ll | 7 ; CHECK-NOT: vcmp
16 ; CHECK-NOT: vcmp
25 ; CHECK-NOT: vcmp
34 ; CHECK-NOT: vcmp
43 ; CHECK-NOT: vcmp
52 ; CHECK-NOT: vcmp
61 ; CHECK-NOT: vcmp
70 ; CHECK-NOT: vcmp
79 ; CHECK-NOT: vcmp
88 ; CHECK-NOT: vcmp
[all …]
|
| D | fast-isel-cmp-imm.ll | 10 ; ARM: vcmp.f32 s{{[0-9]+}}, #0
11 ; THUMB: vcmp.f32 s{{[0-9]+}}, #0
31 ; ARM: vcmp.f32 s{{[0-9]+}}, s{{[0-9]+}}
33 ; THUMB: vcmp.f32 s{{[0-9]+}}, s{{[0-9]+}}
49 ; ARM: vcmp.f64 d{{[0-9]+}}, #0
50 ; THUMB: vcmp.f64 d{{[0-9]+}}, #0
68 ; ARM: vcmp.f64 d{{[0-9]+}}, d{{[0-9]+}}
70 ; THUMB: vcmp.f64 d{{[0-9]+}}, d{{[0-9]+}}
|
| D | fpcmp-opt.ll | 13 ; CHECK: vcmp.f32 [[S1]], [[S0]]
41 ; CHECK-NOT: vcmp.f32
64 ; CHECK-NOT: vcmp.f32
|
| D | fpcmp.ll | 15 ;CHECK: vcmp.f32
55 ;CHECK: vcmp.f32
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vminmaxnm.ll | 7 ; CHECK-NOT: vcmp
16 ; CHECK-NOT: vcmp
25 ; CHECK-NOT: vcmp
34 ; CHECK-NOT: vcmp
43 ; CHECK-NOT: vcmp
52 ; CHECK-NOT: vcmp
61 ; CHECK-NOT: vcmp
70 ; CHECK-NOT: vcmp
79 ; CHECK-NOT: vcmp
88 ; CHECK-NOT: vcmp
[all …]
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | fp.cmp.ll | 65 ; ARM32: vcmp.f32
71 ; ARM32: vcmp.f64
131 ; ARM32: vcmp.f32
136 ; ARM32: vcmp.f64
186 ; ARM32: vcmp.f32
191 ; ARM32: vcmp.f64
241 ; ARM32: vcmp.f32
246 ; ARM32: vcmp.f64
296 ; ARM32: vcmp.f32
301 ; ARM32: vcmp.f64
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/ |
| D | float-cmp.ll | 18 ; HARD: vcmp.f32
59 ; HARD: vcmp.f32
77 ; HARD: vcmp.f32
126 ; HARD: vcmp.f32
158 ; DP: vcmp.f64
205 ; DP: vcmp.f64
263 ; DP: vcmp.f64
294 ; DP: vcmp.f64
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | simple-fp-encoding.s | 41 vcmp.f64 d17, d16
42 vcmp.f32 s1, s0
44 @ CHECK: vcmp.f64 d17, d16 @ encoding: [0x60,0x1b,0xf4,0xee]
45 @ CHECK: vcmp.f32 s1, s0 @ encoding: [0x40,0x0a,0xf4,0xee]
47 vcmp.f64 d17, #0.0
48 vcmp.f32 s1, #0.0
50 @ CHECK: vcmp.f64 d17, #0 @ encoding: [0x40,0x1b,0xf5,0xee]
51 @ CHECK: vcmp.f32 s1, #0 @ encoding: [0x40,0x0a,0xf5,0xee]
|
| D | fullfp16.s | 40 vcmp.f16 s0, s1
41 @ ARM: vcmp.f16 s0, s1 @ encoding: [0x60,0x09,0xb4,0xee]
42 @ THUMB: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
44 vcmp.f16 s2, #0
45 @ ARM: vcmp.f16 s2, #0 @ encoding: [0x40,0x19,0xb5,0xee]
46 @ THUMB: vcmp.f16 s2, #0 @ encoding: [0xb5,0xee,0x40,0x19]
|
| D | single-precision-fp.s | 57 vcmp.f64 d2, d3
60 vcmp.f64 d6, #0
64 @ CHECK-ERRORS-NEXT: vcmp.f64 d2, d3
70 @ CHECK-ERRORS-NEXT: vcmp.f64 d6, #0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/ |
| D | arm-isel-fp.ll | 72 ; HARD: vcmp.f32
85 ; HARD: vcmp.f32
88 ; HARD-NOT: vcmp
|
| /external/llvm/test/MC/ARM/ |
| D | fullfp16.s | 40 vcmp.f16 s0, s1
41 @ ARM: vcmp.f16 s0, s1 @ encoding: [0x60,0x09,0xb4,0xee]
42 @ THUMB: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
44 vcmp.f16 s2, #0
45 @ ARM: vcmp.f16 s2, #0 @ encoding: [0x40,0x19,0xb5,0xee]
46 @ THUMB: vcmp.f16 s2, #0 @ encoding: [0xb5,0xee,0x40,0x19]
|
| D | single-precision-fp.s | 57 vcmp.f64 d2, d3
60 vcmp.f64 d6, #0
64 @ CHECK-ERRORS-NEXT: vcmp.f64 d2, d3
70 @ CHECK-ERRORS-NEXT: vcmp.f64 d6, #0
|
| /external/compiler-rt/lib/builtins/arm/ |
| D | gesf2vfp.S | 24 vcmp.f32 s14, s15
|