Searched refs:view_mask (Results 1 – 12 of 12) sorted by relevance
| /external/mesa3d/src/intel/vulkan/ |
| D | anv_nir_lower_multiview.c | 38 uint32_t view_mask; member
60 nir_imm_int(b, _mesa_bitcount(state->view_mask))); in build_instance_id()
74 assert(state->view_mask != 0); in build_view_index()
75 if (0 && _mesa_bitcount(state->view_mask) == 1) { in build_view_index()
76 state->view_index = nir_imm_int(b, ffs(state->view_mask) - 1); in build_view_index()
79 assert((state->view_mask & 0xffff0000) == 0); in build_view_index()
87 nir_imm_int(b, _mesa_bitcount(state->view_mask))); in build_view_index()
89 if (0 && util_is_power_of_two(state->view_mask + 1)) { in build_view_index()
99 for_each_bit(bit, state->view_mask) { in build_view_index()
155 anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask) in anv_nir_lower_multiview() argument
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| D | anv_nir.h | 38 bool anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask);
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| D | genX_query.c | 484 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) { in genX()
486 _mesa_bitcount(cmd_buffer->state.subpass->view_mask); in genX()
541 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) { in genX()
543 _mesa_bitcount(cmd_buffer->state.subpass->view_mask); in genX()
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| D | anv_pass.c | 112 subpass->view_mask = 0; in anv_CreateRenderPass()
281 pass->subpasses[i].view_mask = mv->pViewMasks[i]; in anv_CreateRenderPass()
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| D | anv_pipeline.c | 363 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask, in anv_pipeline_hash_shader()
364 sizeof(pipeline->subpass->view_mask)); in anv_pipeline_hash_shader()
406 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask); in anv_pipeline_compile()
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| D | anv_blorp.c | 971 if (subpass->view_mask) { in clear_color_attachment()
973 for_each_bit(view_idx, subpass->view_mask) { in clear_color_attachment()
1039 if (subpass->view_mask) { in clear_depth_stencil_attachment()
1041 for_each_bit(view_idx, subpass->view_mask) { in clear_depth_stencil_attachment()
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| D | anv_private.h | 2812 uint32_t view_mask; member
2824 return MAX2(1, _mesa_bitcount(subpass->view_mask)); in anv_subpass_view_count()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_pass.c | 114 subpass->view_mask = multiview_info->pViewMasks[i]; in radv_CreateRenderPass()
124 pass->attachments[desc->pInputAttachments[j].attachment].view_mask |= subpass->view_mask; in radv_CreateRenderPass()
136 pass->attachments[desc->pColorAttachments[j].attachment].view_mask |= subpass->view_mask; in radv_CreateRenderPass()
151 pass->attachments[desc->pResolveAttachments[j].attachment].view_mask |= subpass->view_mask; in radv_CreateRenderPass()
160 pass->attachments[desc->pDepthStencilAttachment->attachment].view_mask |= subpass->view_mask; in radv_CreateRenderPass()
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| D | radv_meta_clear.c | 332 uint32_t view_mask) in emit_color_clear() argument
391 if (view_mask) { in emit_color_clear()
393 for_each_bit(i, view_mask) in emit_color_clear()
945 uint32_t view_mask) in emit_fast_color_clear() argument
989 if (view_mask && (iview->image->info.array_size >= 32 || in emit_fast_color_clear()
990 (1u << iview->image->info.array_size) - 1u != view_mask)) in emit_fast_color_clear()
992 if (!view_mask && clear_rect->baseArrayLayer != 0) in emit_fast_color_clear()
994 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size) in emit_fast_color_clear()
1056 uint32_t view_mask) in emit_clear() argument
1060 pre_flush, post_flush, view_mask)) in emit_clear()
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| D | radv_private.h | 1624 uint32_t view_mask; member
1634 uint32_t view_mask; member
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| D | radv_cmd_buffer.c | 3321 if (!state->subpass->view_mask) { in radv_emit_draw_packets()
3329 for_each_bit(i, state->subpass->view_mask) { in radv_emit_draw_packets()
3368 if (!state->subpass->view_mask) { in radv_emit_draw_packets()
3374 for_each_bit(i, state->subpass->view_mask) { in radv_emit_draw_packets()
3383 if (!state->subpass->view_mask) { in radv_emit_draw_packets()
3387 for_each_bit(i, state->subpass->view_mask) { in radv_emit_draw_packets()
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| D | radv_pipeline.c | 2439 if (subpass->view_mask) in radv_pipeline_init()
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