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Searched refs:vram (Results 1 – 25 of 28) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeon/
Dr600_cs.h44 uint64_t vram, uint64_t gtt) in radeon_cs_memory_below_limit() argument
46 vram += cs->used_vram; in radeon_cs_memory_below_limit()
50 if (vram > screen->info.vram_size) in radeon_cs_memory_below_limit()
51 gtt += vram - screen->info.vram_size; in radeon_cs_memory_below_limit()
107 rctx->vram + rbo->vram_usage, in radeon_add_to_buffer_list_check_mem()
Dr600_pipe_common.c172 uint64_t vram = ctx->dma.cs->used_vram; in si_need_dma_space() local
176 vram += dst->vram_usage; in si_need_dma_space()
180 vram += src->vram_usage; in si_need_dma_space()
209 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) { in si_need_dma_space()
Dr600_pipe_common.h412 uint64_t vram; member
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h46 uint64_t vram, uint64_t gtt) in radeon_cs_memory_below_limit() argument
48 vram += cs->used_vram; in radeon_cs_memory_below_limit()
52 if (vram > screen->info.vram_size) in radeon_cs_memory_below_limit()
53 gtt += vram - screen->info.vram_size; in radeon_cs_memory_below_limit()
109 rctx->vram + rbo->vram_usage, in radeon_add_to_buffer_list_check_mem()
Dr600_hw_context.c41 ctx->b.vram, ctx->b.gtt)) { in r600_need_cs_space()
43 ctx->b.vram = 0; in r600_need_cs_space()
49 ctx->b.vram = 0; in r600_need_cs_space()
337 ctx->b.vram = 0; in r600_begin_new_cs()
Dr600_pipe_common.c253 uint64_t vram = ctx->dma.cs->used_vram; in r600_need_dma_space() local
257 vram += dst->vram_usage; in r600_need_dma_space()
261 vram += src->vram_usage; in r600_need_dma_space()
290 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) { in r600_need_dma_space()
Dr600_pipe_common.h531 uint64_t vram; member
835 rctx->vram += res->vram_usage; in r600_context_add_resource_size()
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_compute.c76 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
92 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
124 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
131 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
138 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
145 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
148 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
Dnv98_video.c91 struct nv04_fifo nv04_data = {.vram = 0xbeef0201, .gart = 0xbeef0202}; in nv98_create_decoder()
166 PUSH_DATA (push[0], nv04_data.vram); in nv98_create_decoder()
173 PUSH_DATA (push[1], nv04_data.vram); in nv98_create_decoder()
180 PUSH_DATA (push[2], nv04_data.vram); in nv98_create_decoder()
Dnv50_screen.c556 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
557 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
563 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
564 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
565 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
587 PUSH_DATA(push, fifo->vram); in nv50_screen_init_hwctx()
590 PUSH_DATA(push, fifo->vram); in nv50_screen_init_hwctx()
Dnv84_video.c274 struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 }; in nv84_create_decoder()
515 PUSH_DATA(bsp_push, nv04_data.vram); in nv84_create_decoder()
517 PUSH_DATA (bsp_push, nv04_data.vram); in nv84_create_decoder()
537 PUSH_DATA(vp_push, nv04_data.vram); in nv84_create_decoder()
540 PUSH_DATA (vp_push, nv04_data.vram); in nv84_create_decoder()
/external/mesa3d/src/mesa/drivers/dri/nouveau/
Dnv04_context.c88 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
89 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
95 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
103 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
Dnv20_context.c109 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
112 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
113 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
115 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
173 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
175 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
Dnv04_surface.c234 PUSH_DATA (push, fifo->vram); in nv04_surface_copy_swizzle()
242 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_copy_swizzle()
298 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_copy_m2mf()
299 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_copy_m2mf()
441 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_fill()
442 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_fill()
Dnv10_context.c214 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
218 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
219 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
250 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
251 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
Dnouveau_context.c144 .vram = 0xbeef0201, in nouveau_context_init()
/external/mesa3d/src/gallium/drivers/nouveau/nv30/
Dnv30_screen.c646 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */ in nv30_screen_create()
648 PUSH_DATA (push, fifo->vram); /* COLOR1 */ in nv30_screen_create()
650 PUSH_DATA (push, fifo->vram); /* COLOR0 */ in nv30_screen_create()
651 PUSH_DATA (push, fifo->vram); /* ZETA */ in nv30_screen_create()
652 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */ in nv30_screen_create()
678 PUSH_DATA (push, fifo->vram); in nv30_screen_create()
679 PUSH_DATA (push, fifo->vram); /* COLOR3 */ in nv30_screen_create()
Dnv30_transfer.c440 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
441 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
451 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
461 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
513 PUSH_DATA (push, (src->domain == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_rect_m2mf()
514 PUSH_DATA (push, (dst->domain == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_rect_m2mf()
704 PUSH_DATA (push, (s_dom == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_copy_data()
705 PUSH_DATA (push, (d_dom == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_copy_data()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_hw_context.c53 ctx->b.vram, ctx->b.gtt))) { in si_need_cs_space()
55 ctx->b.vram = 0; in si_need_cs_space()
60 ctx->b.vram = 0; in si_need_cs_space()
/external/mesa3d/src/amd/common/
Dac_gpu_info.c100 struct amdgpu_heap_info vram, vram_vis, gtt; in ac_query_gpu_info() local
133 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram); in ac_query_gpu_info()
270 info->vram_size = vram.heap_size; in ac_query_gpu_info()
/external/mesa3d/src/gallium/drivers/nouveau/
Dnouveau_screen.c171 struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 }; in nouveau_screen_init()
Dnouveau_video.c503 struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 }; in nouveau_create_decoder()
603 PUSH_DATA (push, nv04_data.vram); in nouveau_create_decoder()
619 PUSH_DATA (push, nv04_data.vram); in nouveau_create_decoder()
/external/libdrm/nouveau/
Dnouveau.h245 uint32_t vram; member
Dabi16.c40 .fb_ctxdma_handle = nv04->vram, in abi16_chan_nv04()
/external/libdrm/include/drm/
Damdgpu_drm.h793 struct drm_amdgpu_heap_info vram; member

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