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Searched refs:vrev64 (Results 1 – 25 of 64) sorted by relevance

123

/external/libhevc/common/arm/
Dihevc_intra_pred_chroma_mode2.s128 vrev64.8 d16,d0
129 vrev64.8 d17,d1
146 vrev64.8 d18,d2
147 vrev64.8 d19,d3
150 vrev64.8 d20,d4
151 vrev64.8 d21,d5
154 vrev64.8 d22,d6
155 vrev64.8 d23,d7
157 vrev64.8 d24,d8
158 vrev64.8 d25,d9
[all …]
Dihevc_intra_pred_luma_mode2.s142 vrev64.8 d8,d0
143 vrev64.8 d9,d1
146 vrev64.8 d10,d2
147 vrev64.8 d11,d3
150 vrev64.8 d12,d4
153 vrev64.8 d13,d5
154 vrev64.8 d14,d6
155 vrev64.8 d15,d7
200 vrev64.8 d8,d0
203 vrev64.8 d9,d1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dbig-endian-vector-callee.ll33 ; SOFT: vrev64.32 [[REG]]
34 ; HARD: vrev64.32 d{{[0-9]+}}, d0
46 ; SOFT: vrev64.32 [[REG]]
47 ; HARD: vrev64.32 d{{[0-9]+}}, d0
59 ; SOFT: vrev64.16 [[REG]]
60 ; HARD: vrev64.16 d{{[0-9]+}}, d0
72 ; SOFT: vrev64.8 [[REG]]
73 ; HARD: vrev64.8 d{{[0-9]+}}, d0
112 ; SOFT: vrev64.32 [[REG]]
113 ; HARD: vrev64.32 d{{[0-9]+}}, d0
[all …]
Dbig-endian-vector-caller.ll39 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
41 ; HARD: vrev64.32 d0
55 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
57 ; HARD: vrev64.32 d0
71 ; SOFT: vrev64.16 [[REG:d[0-9]+]]
73 ; HARD: vrev64.16 d0
87 ; SOFT: vrev64.8 [[REG:d[0-9]+]]
89 ; HARD: vrev64.8 d0
136 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
138 ; HARD: vrev64.32 d0
[all …]
Dbig-endian-neon-bitconv.ll20 ; CHECK: vrev64.8
30 ; CHECK: vrev64.8
41 ; CHECK: vrev64.16
51 ; CHECK: vrev64.16
62 ; CHECK: vrev64.32
72 ; CHECK: vrev64.32
83 ; CHECK: vrev64.32
93 ; CHECK: vrev64.32
104 ; CHECK: vrev64.8
114 ; CHECK: vrev64.8
[all …]
Dvrev.ll5 ;CHECK: vrev64.8
13 ;CHECK: vrev64.16
21 ;CHECK: vrev64.32
29 ;CHECK: vrev64.32
37 ;CHECK: vrev64.8
45 ;CHECK: vrev64.16
53 ;CHECK: vrev64.32
61 ;CHECK: vrev64.32
119 ;CHECK: vrev64.8
138 ;CHECK: vrev64.32
[all …]
Dfp16-intrinsic-vector-1op.ll14 ; CHECK-HARD-BE: vrev64.16 [[Q8:q[0-9]+]], q0
16 ; CHECK-HARD-BE-NEXT: vrev64.16 q0, [[Q8]]
28 ; CHECK-SOFTFP-BE: vrev64.16 [[Q8:q[0-9]+]], [[Q8]]
30 ; CHECK-SOFTFP-BE: vrev64.16 [[Q8]], [[Q8]]
Dload_store_multiple.ll12 ;CHECK-BE: vrev64.8 [[Q1:q[0-9]+]], [[Q2:q[0-9]+]]
13 ;CHECK-BE: vrev64.8 [[Q1]], [[Q2]]
29 ;CHECK-BE: vrev64.16 [[Q1:q[0-9]+]], [[Q2:q[0-9]+]]
30 ;CHECK-BE: vrev64.16 [[Q1]], [[Q2]]
Dbig-endian-neon-extend.ll39 ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
53 ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
85 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
99 ; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]
/external/llvm/test/CodeGen/ARM/
Dbig-endian-vector-callee.ll33 ; SOFT: vrev64.32 [[REG]]
34 ; HARD: vrev64.32 d{{[0-9]+}}, d0
46 ; SOFT: vrev64.32 [[REG]]
47 ; HARD: vrev64.32 d{{[0-9]+}}, d0
59 ; SOFT: vrev64.16 [[REG]]
60 ; HARD: vrev64.16 d{{[0-9]+}}, d0
72 ; SOFT: vrev64.8 [[REG]]
73 ; HARD: vrev64.8 d{{[0-9]+}}, d0
112 ; SOFT: vrev64.32 [[REG]]
113 ; HARD: vrev64.32 d{{[0-9]+}}, d0
[all …]
Dbig-endian-vector-caller.ll39 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
41 ; HARD: vrev64.32 d0
55 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
57 ; HARD: vrev64.32 d0
71 ; SOFT: vrev64.16 [[REG:d[0-9]+]]
73 ; HARD: vrev64.16 d0
87 ; SOFT: vrev64.8 [[REG:d[0-9]+]]
89 ; HARD: vrev64.8 d0
136 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
138 ; HARD: vrev64.32 d0
[all …]
Dbig-endian-neon-bitconv.ll20 ; CHECK: vrev64.8
30 ; CHECK: vrev64.8
41 ; CHECK: vrev64.16
51 ; CHECK: vrev64.16
62 ; CHECK: vrev64.32
72 ; CHECK: vrev64.32
83 ; CHECK: vrev64.32
93 ; CHECK: vrev64.32
104 ; CHECK: vrev64.8
114 ; CHECK: vrev64.8
[all …]
Dvrev.ll5 ;CHECK: vrev64.8
13 ;CHECK: vrev64.16
21 ;CHECK: vrev64.32
29 ;CHECK: vrev64.32
37 ;CHECK: vrev64.8
45 ;CHECK: vrev64.16
53 ;CHECK: vrev64.32
61 ;CHECK: vrev64.32
119 ;CHECK: vrev64.8
138 ;CHECK: vrev64.32
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-reverse-encoding.s3 @ CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xf3]
4 vrev64.8 d16, d16
5 @ CHECK: vrev64.16 d16, d16 @ encoding: [0x20,0x00,0xf4,0xf3]
6 vrev64.16 d16, d16
7 @ CHECK: vrev64.32 d16, d16 @ encoding: [0x20,0x00,0xf8,0xf3]
8 vrev64.32 d16, d16
9 @ CHECK: vrev64.8 q8, q8 @ encoding: [0x60,0x00,0xf0,0xf3]
10 vrev64.8 q8, q8
11 @ CHECK: vrev64.16 q8, q8 @ encoding: [0x60,0x00,0xf4,0xf3]
12 vrev64.16 q8, q8
[all …]
Dneont2-reverse-encoding.s3 @ CHECK: vrev64.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x00]
4 vrev64.8 d16, d16
5 @ CHECK: vrev64.16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x00]
6 vrev64.16 d16, d16
7 @ CHECK: vrev64.32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x00]
8 vrev64.32 d16, d16
9 @ CHECK: vrev64.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x00]
10 vrev64.8 q8, q8
11 @ CHECK: vrev64.16 q8, q8 @ encoding: [0xf4,0xff,0x60,0x00]
12 vrev64.16 q8, q8
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-reverse-encoding.s3 @ CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xf3]
4 vrev64.8 d16, d16
5 @ CHECK: vrev64.16 d16, d16 @ encoding: [0x20,0x00,0xf4,0xf3]
6 vrev64.16 d16, d16
7 @ CHECK: vrev64.32 d16, d16 @ encoding: [0x20,0x00,0xf8,0xf3]
8 vrev64.32 d16, d16
9 @ CHECK: vrev64.8 q8, q8 @ encoding: [0x60,0x00,0xf0,0xf3]
10 vrev64.8 q8, q8
11 @ CHECK: vrev64.16 q8, q8 @ encoding: [0x60,0x00,0xf4,0xf3]
12 vrev64.16 q8, q8
[all …]
Dneont2-reverse-encoding.s3 @ CHECK: vrev64.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x00]
4 vrev64.8 d16, d16
5 @ CHECK: vrev64.16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x00]
6 vrev64.16 d16, d16
7 @ CHECK: vrev64.32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x00]
8 vrev64.32 d16, d16
9 @ CHECK: vrev64.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x00]
10 vrev64.8 q8, q8
11 @ CHECK: vrev64.16 q8, q8 @ encoding: [0xf4,0xff,0x60,0x00]
12 vrev64.16 q8, q8
[all …]
/external/llvm/test/MC/ARM/
Dneon-reverse-encoding.s3 @ CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xf3]
4 vrev64.8 d16, d16
5 @ CHECK: vrev64.16 d16, d16 @ encoding: [0x20,0x00,0xf4,0xf3]
6 vrev64.16 d16, d16
7 @ CHECK: vrev64.32 d16, d16 @ encoding: [0x20,0x00,0xf8,0xf3]
8 vrev64.32 d16, d16
9 @ CHECK: vrev64.8 q8, q8 @ encoding: [0x60,0x00,0xf0,0xf3]
10 vrev64.8 q8, q8
11 @ CHECK: vrev64.16 q8, q8 @ encoding: [0x60,0x00,0xf4,0xf3]
12 vrev64.16 q8, q8
[all …]
Dneont2-reverse-encoding.s3 @ CHECK: vrev64.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x00]
4 vrev64.8 d16, d16
5 @ CHECK: vrev64.16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x00]
6 vrev64.16 d16, d16
7 @ CHECK: vrev64.32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x00]
8 vrev64.32 d16, d16
9 @ CHECK: vrev64.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x00]
10 vrev64.8 q8, q8
11 @ CHECK: vrev64.16 q8, q8 @ encoding: [0xf4,0xff,0x60,0x00]
12 vrev64.16 q8, q8
[all …]
/external/capstone/suite/MC/ARM/
Dneon-reverse-encoding.s.cs2 0x20,0x00,0xf0,0xf3 = vrev64.8 d16, d16
3 0x20,0x00,0xf4,0xf3 = vrev64.16 d16, d16
4 0x20,0x00,0xf8,0xf3 = vrev64.32 d16, d16
5 0x60,0x00,0xf0,0xf3 = vrev64.8 q8, q8
6 0x60,0x00,0xf4,0xf3 = vrev64.16 q8, q8
7 0x60,0x00,0xf8,0xf3 = vrev64.32 q8, q8
Dneont2-reverse-encoding.s.cs2 0xf0,0xff,0x20,0x00 = vrev64.8 d16, d16
3 0xf4,0xff,0x20,0x00 = vrev64.16 d16, d16
4 0xf8,0xff,0x20,0x00 = vrev64.32 d16, d16
5 0xf0,0xff,0x60,0x00 = vrev64.8 q8, q8
6 0xf4,0xff,0x60,0x00 = vrev64.16 q8, q8
7 0xf8,0xff,0x60,0x00 = vrev64.32 q8, q8
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvrev.ll5 ;CHECK: vrev64.8
13 ;CHECK: vrev64.16
21 ;CHECK: vrev64.32
29 ;CHECK: vrev64.32
37 ;CHECK: vrev64.8
45 ;CHECK: vrev64.16
53 ;CHECK: vrev64.32
61 ;CHECK: vrev64.32
119 ;CHECK: vrev64.8
138 ;CHECK: vrev64.32
[all …]
/external/boringssl/ios-arm/crypto/fipsmodule/
Dghashv8-armx32.S85 vrev64.8 q9,q9
110 vrev64.8 q0,q0
149 vrev64.8 q8,q8
150 vrev64.8 q0,q0
156 vrev64.8 q9,q9
188 vrev64.8 q8,q8
194 vrev64.8 q9,q9
244 vrev64.8 q0,q0
/external/boringssl/linux-arm/crypto/fipsmodule/
Dghashv8-armx32.S82 vrev64.8 q9,q9
107 vrev64.8 q0,q0
144 vrev64.8 q8,q8
145 vrev64.8 q0,q0
151 vrev64.8 q9,q9
183 vrev64.8 q8,q8
189 vrev64.8 q9,q9
239 vrev64.8 q0,q0
/external/libxaac/decoder/armv7/
Dixheaacd_esbr_cos_sin_mod_loop1.s40 vrev64.32 d1, d0
66 vrev64.32 d1, d0
92 vrev64.32 d1, d0
118 vrev64.32 d1, d0

123