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Searched refs:vshr (Results 1 – 25 of 75) sorted by relevance

123

/external/capstone/suite/MC/ARM/
Dneon-shift-encoding.s.cs18 0x30,0x00,0xc9,0xf3 = vshr.u8 d16, d16, #7
19 0x30,0x00,0xd1,0xf3 = vshr.u16 d16, d16, #15
20 0x30,0x00,0xe1,0xf3 = vshr.u32 d16, d16, #31
21 0xb0,0x00,0xc1,0xf3 = vshr.u64 d16, d16, #63
22 0x70,0x00,0xc9,0xf3 = vshr.u8 q8, q8, #7
23 0x70,0x00,0xd1,0xf3 = vshr.u16 q8, q8, #15
24 0x70,0x00,0xe1,0xf3 = vshr.u32 q8, q8, #31
25 0xf0,0x00,0xc1,0xf3 = vshr.u64 q8, q8, #63
26 0x30,0x00,0xc9,0xf2 = vshr.s8 d16, d16, #7
27 0x30,0x00,0xd1,0xf2 = vshr.s16 d16, d16, #15
[all …]
Dneont2-shift-encoding.s.cs18 0xc8,0xff,0x30,0x00 = vshr.u8 d16, d16, #8
19 0xd0,0xff,0x30,0x00 = vshr.u16 d16, d16, #16
20 0xe0,0xff,0x30,0x00 = vshr.u32 d16, d16, #32
21 0xc0,0xff,0xb0,0x00 = vshr.u64 d16, d16, #64
22 0xc8,0xff,0x70,0x00 = vshr.u8 q8, q8, #8
23 0xd0,0xff,0x70,0x00 = vshr.u16 q8, q8, #16
24 0xe0,0xff,0x70,0x00 = vshr.u32 q8, q8, #32
25 0xc0,0xff,0xf0,0x00 = vshr.u64 q8, q8, #64
26 0xc8,0xef,0x30,0x00 = vshr.s8 d16, d16, #8
27 0xd0,0xef,0x30,0x00 = vshr.s16 d16, d16, #16
[all …]
/external/llvm/test/MC/ARM/
Dneon-shift-encoding.s39 vshr.u8 d16, d16, #7
40 vshr.u16 d16, d16, #15
41 vshr.u32 d16, d16, #31
42 vshr.u64 d16, d16, #63
43 vshr.u8 q8, q8, #7
44 vshr.u16 q8, q8, #15
45 vshr.u32 q8, q8, #31
46 vshr.u64 q8, q8, #63
47 vshr.s8 d16, d16, #7
48 vshr.s16 d16, d16, #15
[all …]
Dneont2-shift-encoding.s37 @ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0xc8,0xff,0x30,0x00]
38 vshr.u8 d16, d16, #8
39 @ CHECK: vshr.u16 d16, d16, #16 @ encoding: [0xd0,0xff,0x30,0x00]
40 vshr.u16 d16, d16, #16
41 @ CHECK: vshr.u32 d16, d16, #32 @ encoding: [0xe0,0xff,0x30,0x00]
42 vshr.u32 d16, d16, #32
43 @ CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x00]
44 vshr.u64 d16, d16, #64
45 @ CHECK: vshr.u8 q8, q8, #8 @ encoding: [0xc8,0xff,0x70,0x00]
46 vshr.u8 q8, q8, #8
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-shift-encoding.s39 vshr.u8 d16, d16, #7
40 vshr.u16 d16, d16, #15
41 vshr.u32 d16, d16, #31
42 vshr.u64 d16, d16, #63
43 vshr.u8 q8, q8, #7
44 vshr.u16 q8, q8, #15
45 vshr.u32 q8, q8, #31
46 vshr.u64 q8, q8, #63
47 vshr.s8 d16, d16, #7
48 vshr.s16 d16, d16, #15
[all …]
Dneont2-shift-encoding.s37 @ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0xc8,0xff,0x30,0x00]
38 vshr.u8 d16, d16, #8
39 @ CHECK: vshr.u16 d16, d16, #16 @ encoding: [0xd0,0xff,0x30,0x00]
40 vshr.u16 d16, d16, #16
41 @ CHECK: vshr.u32 d16, d16, #32 @ encoding: [0xe0,0xff,0x30,0x00]
42 vshr.u32 d16, d16, #32
43 @ CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x00]
44 vshr.u64 d16, d16, #64
45 @ CHECK: vshr.u8 q8, q8, #8 @ encoding: [0xc8,0xff,0x70,0x00]
46 vshr.u8 q8, q8, #8
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-shift-encoding.s37 @ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0xc8,0xff,0x30,0x00]
38 vshr.u8 d16, d16, #8
39 @ CHECK: vshr.u16 d16, d16, #16 @ encoding: [0xd0,0xff,0x30,0x00]
40 vshr.u16 d16, d16, #16
41 @ CHECK: vshr.u32 d16, d16, #32 @ encoding: [0xe0,0xff,0x30,0x00]
42 vshr.u32 d16, d16, #32
43 @ CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x00]
44 vshr.u64 d16, d16, #64
45 @ CHECK: vshr.u8 q8, q8, #8 @ encoding: [0xc8,0xff,0x70,0x00]
46 vshr.u8 q8, q8, #8
[all …]
Dneon-shift-encoding.s36 @ CHECK: vshr.u8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf3]
37 vshr.u8 d16, d16, #7
38 @ CHECK: vshr.u16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf3]
39 vshr.u16 d16, d16, #15
40 @ CHECK: vshr.u32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf3]
41 vshr.u32 d16, d16, #31
42 @ CHECK: vshr.u64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf3]
43 vshr.u64 d16, d16, #63
44 @ CHECK: vshr.u8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf3]
45 vshr.u8 q8, q8, #7
[all …]
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_vert.s200 @vshr.s16 q0, q0, #1
201 @vshr.s16 q14, q14, #1
233 vshr.s64 d24, d24, #8
236 vshr.s64 d25, d25, #8
243 vshr.s64 d24, d24, #8
246 vshr.s64 d25, d25, #8
268 vshr.s64 d24, d24, #8
271 vshr.s64 d25, d25, #8
281 vshr.s64 d24, d24, #8
284 vshr.s64 d25, d25, #8
[all …]
Dihevc_intra_pred_luma_dc.s137 vshr.s64 d8, d8, #32
206 vshr.u16 d15, d14, #2 @final dst[0]'s value in d15[0]
482 vshr.s64 d3, d3, #40 @row 0 shift (prol) (first value to be ignored)
487 vshr.s64 d3, d3, #8 @row 1 shift (prol)
495 vshr.s64 d3, d3, #8 @row 2 shift (prol)
Dihevc_intra_pred_luma_horz.s207 vshr.s16 q12,q12,#1
221 vshr.s16 q12,q12,#1
285 vshr.s16 q12,q12,#1
326 vshr.s16 q12,q12,#1
Dihevc_intra_pred_chroma_horz.s214 @vshr.s16 q12,q12,#1
228 @vshr.s16 q12,q12,#1
295 vshr.s16 q12,q12,#1
336 vshr.s16 q12,q12,#1
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Dvec-sh-imm.ll1 ; Show that we know how to translate vshl and vshr with immediate shift amounts.
34 ; ASM-NEXT: vshr.s32 {{.*}}, #31
38 ; IASM-NOT: vshr
50 ; ASM-NEXT: vshr.s16 {{.*}}, #15
54 ; IASM-NOT: vshr
66 ; ASM-NEXT: vshr.s8 {{.*}}, #7
70 ; IASM-NOT: vshr
Dselect-vec.ll32 ; ASM-NEXT: vshr.s32 [[M:.*]], {{.*}}, #31
38 ; IASM-NOT: vshr
53 ; ASM-NEXT: vshr.s32 [[M:.*]], {{.*}}, #31
59 ; IASM-NOT: vshr
74 ; ASM-NEXT: vshr.s16 [[M:.*]], {{.*}}, #15
80 ; IASM-NOT: vshr
96 ; ASM-NEXT: vshr.s8 [[M:.*]], {{.*}}, #7
102 ; IASM-NOT: vshr
/external/boringssl/src/crypto/curve25519/asm/
Dx25519-asm-arm.S57 vshr.u64 q1,q0,#7
58 vshr.u64 q0,q0,#8
92 vshr.u64 q3,q2,#7
93 vshr.u64 q2,q2,#6
109 vshr.u64 q5,q5,#26
110 vshr.u64 q6,q6,#3
111 vshr.u64 q7,q7,#29
112 vshr.u64 q8,q8,#6
113 vshr.u64 q10,q10,#25
114 vshr.u64 q11,q11,#3
[all …]
/external/boringssl/src/crypto/poly1305/
Dpoly1305_arm_asm.S250 # asm 1: vshr.u64 >mask=reg128#7,<mask=reg128#7,#6
251 # asm 2: vshr.u64 >mask=q6,<mask=q6,#6
252 vshr.u64 q6,q6,#6
255 # asm 1: vshr.u64 >u4=reg128#8,<u4=reg128#8,#7
256 # asm 2: vshr.u64 >u4=q7,<u4=q7,#7
257 vshr.u64 q7,q7,#7
700 # asm 1: vshr.u64 >v4=reg128#4,<d23=reg128#2,#40
701 # asm 2: vshr.u64 >v4=q3,<d23=q1,#40
702 vshr.u64 q3,q1,#40
949 # asm 1: vshr.u64 >t1=reg128#4,<r0=reg128#8,#26
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvshift.ll181 ;CHECK: vshr.u8
189 ;CHECK: vshr.u16
197 ;CHECK: vshr.u32
205 ;CHECK: vshr.u64
253 ;CHECK: vshr.u8
261 ;CHECK: vshr.u16
269 ;CHECK: vshr.u32
277 ;CHECK: vshr.u64
332 ;CHECK: vshr.s8
340 ;CHECK: vshr.s16
[all …]
Dvshl.ll218 ;CHECK: vshr.s8
226 ;CHECK: vshr.s16
234 ;CHECK: vshr.s32
242 ;CHECK: vshr.s64
250 ;CHECK: vshr.u8
258 ;CHECK: vshr.u16
266 ;CHECK: vshr.u32
274 ;CHECK: vshr.u64
282 ;CHECK: vshr.s8
290 ;CHECK: vshr.s16
[all …]
/external/llvm/test/CodeGen/ARM/
Dvshift.ll181 ;CHECK: vshr.u8
189 ;CHECK: vshr.u16
197 ;CHECK: vshr.u32
205 ;CHECK: vshr.u64
253 ;CHECK: vshr.u8
261 ;CHECK: vshr.u16
269 ;CHECK: vshr.u32
277 ;CHECK: vshr.u64
332 ;CHECK: vshr.s8
340 ;CHECK: vshr.s16
[all …]
Dvshrn.ll32 ; CHECK: vshr.s16
42 ; CHECK: vshr.u32
52 ; CHECK: vshr.u64
Dvshl.ll218 ;CHECK: vshr.s8
226 ;CHECK: vshr.s16
234 ;CHECK: vshr.s32
242 ;CHECK: vshr.s64
250 ;CHECK: vshr.u8
258 ;CHECK: vshr.u16
266 ;CHECK: vshr.u32
274 ;CHECK: vshr.u64
282 ;CHECK: vshr.s8
290 ;CHECK: vshr.s16
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvshift.ll181 ;CHECK: vshr.u8
189 ;CHECK: vshr.u16
197 ;CHECK: vshr.u32
205 ;CHECK: vshr.u64
253 ;CHECK: vshr.u8
261 ;CHECK: vshr.u16
269 ;CHECK: vshr.u32
277 ;CHECK: vshr.u64
332 ;CHECK: vshr.s8
340 ;CHECK: vshr.s16
[all …]
Dvshrn.ll32 ; CHECK: vshr.s16
42 ; CHECK: vshr.u32
52 ; CHECK: vshr.u64
Dvshl.ll218 ;CHECK: vshr.s8
226 ;CHECK: vshr.s16
234 ;CHECK: vshr.s32
242 ;CHECK: vshr.s64
250 ;CHECK: vshr.u8
258 ;CHECK: vshr.u16
266 ;CHECK: vshr.u32
274 ;CHECK: vshr.u64
282 ;CHECK: vshr.s8
290 ;CHECK: vshr.s16
[all …]
/external/libavc/common/arm/
Dih264_iquant_itrans_recon_a9.s172 vshr.s16 d8, d1, #1 @q0>>1
173 vshr.s16 d9, d3, #1 @q1>>1
197 vshr.s16 d18, d11, #1 @q0>>1
198 vshr.s16 d19, d13, #1 @q1>>1
346 vshr.s16 d8, d1, #1 @q0>>1
347 vshr.s16 d9, d3, #1 @q1>>1
372 vshr.s16 d18, d11, #1 @q0>>1
373 vshr.s16 d19, d13, #1 @q1>>1
607 vshr.s16 q10, q2, #0x1 @
634 vshr.s16 q6, q3, #0x1 @
[all …]

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