/external/v8/src/ia32/ |
D | disasm-ia32.cc | 737 int mod, regop, rm, vvvv = vex_vreg(); in AVXInstruction() local 742 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 747 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 752 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 757 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 762 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 767 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 772 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 777 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 782 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() [all …]
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/external/v8/src/x64/ |
D | disasm-x64.cc | 885 int mod, regop, rm, vvvv = vex_vreg(); in AVXInstruction() local 890 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 895 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 900 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 905 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 910 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 915 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 920 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 925 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() 930 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); in AVXInstruction() [all …]
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/external/syzkaller/pkg/ifuzz/ |
D | encode.go | 38 var vvvv, vexR, vexX, vexB byte 141 vvvv = 15 143 vvvv = byte(r.Intn(16)) 146 code = append(code, W<<7|vvvv<<3|L<<2|pp) 149 vvvv |= 8 188 if reg|(1-vexR)<<3 == vvvv^0xf { 221 if iiii != vvvv^0xf && iiii != rrrr {
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.cpp | 1559 insn->vvvv = (Reg)fixupRegValue(insn, in fixupReg() 1561 insn->vvvv, in fixupReg() 1704 int vvvv; in readVVVV() local 1706 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | in readVVVV() 1709 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); in readVVVV() 1711 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); in readVVVV() 1713 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); in readVVVV() 1718 vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later. in readVVVV() 1720 insn->vvvv = static_cast<Reg>(vvvv); in readVVVV() 1758 needVVVV = hasVVVV && (insn->vvvv != 0); in readOperands() [all …]
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D | X86DisassemblerDecoder.h | 602 Reg vvvv; member
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/external/swiftshader/src/Pipeline/ |
D | SamplerCore.cpp | 95 Float4 vvvv = v; in sampleTexture() local 109 computeLod(texture, lod, anisotropy, uDelta, vDelta, uuuu, vvvv, bias.x, dsx, dsy, function); in sampleTexture() 114 cubeFace(face, uuuu, vvvv, u, v, w, M); in sampleTexture() 120 computeLod3D(texture, lod, uuuu, vvvv, wwww, bias.x, dsx, dsy, function); in sampleTexture() 125 …c = sampleFilter(texture, uuuu, vvvv, wwww, offset, lod, anisotropy, uDelta, vDelta, face, functio… in sampleTexture() 129 …Vector4f cf = sampleFloatFilter(texture, uuuu, vvvv, wwww, qqqq, offset, lod, anisotropy, uDelta, … in sampleTexture() 259 Float4 vvvv = v; in sampleTexture() local 273 computeLod(texture, lod, anisotropy, uDelta, vDelta, uuuu, vvvv, bias.x, dsx, dsy, function); in sampleTexture() 278 cubeFace(face, uuuu, vvvv, u, v, w, M); in sampleTexture() 284 computeLod3D(texture, lod, uuuu, vvvv, wwww, bias.x, dsx, dsy, function); in sampleTexture() [all …]
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D | SamplerCore.hpp | 80 …void computeIndices(UInt index[4], Short4 uuuu, Short4 vvvv, Short4 wwww, Vector4f &offset, const … 81 …void computeIndices(UInt index[4], Int4& uuuu, Int4& vvvv, Int4& wwww, const Pointer<Byte> &mipmap…
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/external/swiftshader/src/Shader/ |
D | SamplerCore.cpp | 95 Float4 vvvv = v; in sampleTexture() local 109 computeLod(texture, lod, anisotropy, uDelta, vDelta, uuuu, vvvv, bias.x, dsx, dsy, function); in sampleTexture() 114 cubeFace(face, uuuu, vvvv, u, v, w, M); in sampleTexture() 120 computeLod3D(texture, lod, uuuu, vvvv, wwww, bias.x, dsx, dsy, function); in sampleTexture() 125 …c = sampleFilter(texture, uuuu, vvvv, wwww, offset, lod, anisotropy, uDelta, vDelta, face, functio… in sampleTexture() 129 …Vector4f cf = sampleFloatFilter(texture, uuuu, vvvv, wwww, qqqq, offset, lod, anisotropy, uDelta, … in sampleTexture() 304 Float4 vvvv = v; in sampleTexture() local 318 computeLod(texture, lod, anisotropy, uDelta, vDelta, uuuu, vvvv, bias.x, dsx, dsy, function); in sampleTexture() 323 cubeFace(face, uuuu, vvvv, u, v, w, M); in sampleTexture() 329 computeLod3D(texture, lod, uuuu, vvvv, wwww, bias.x, dsx, dsy, function); in sampleTexture() [all …]
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D | SamplerCore.hpp | 80 …void computeIndices(UInt index[4], Short4 uuuu, Short4 vvvv, Short4 wwww, Vector4f &offset, const … 81 …void computeIndices(UInt index[4], Int4& uuuu, Int4& vvvv, Int4& wwww, const Pointer<Byte> &mipmap…
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/external/llvm/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.cpp | 1549 insn->vvvv = (Reg)fixupRegValue(insn, in fixupReg() 1551 insn->vvvv, in fixupReg() 1694 int vvvv; in readVVVV() local 1696 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | in readVVVV() 1699 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); in readVVVV() 1701 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); in readVVVV() 1703 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); in readVVVV() 1708 vvvv &= 0x7; in readVVVV() 1710 insn->vvvv = static_cast<Reg>(vvvv); in readVVVV() 1748 needVVVV = hasVVVV && (insn->vvvv != 0); in readOperands()
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D | X86DisassemblerDecoder.h | 598 Reg vvvv; member
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/external/capstone/arch/X86/ |
D | X86DisassemblerDecoder.c | 1809 insn->vvvv = (Reg)fixupRegValue(insn, in fixupReg() 1811 insn->vvvv, in fixupReg() 1957 int vvvv; in readVVVV() local 1961 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | in readVVVV() 1964 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); in readVVVV() 1966 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); in readVVVV() 1968 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); in readVVVV() 1973 vvvv &= 0x7; in readVVVV() 1975 insn->vvvv = vvvv; in readVVVV() 2016 needVVVV = hasVVVV && (insn->vvvv != 0); in readOperands()
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D | X86DisassemblerDecoder.h | 674 Reg vvvv; member
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D | X86Disassembler.c | 671 translateRegister(mcInst, insn->vvvv); in translateOperand()
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/X86/ |
D | invalid-VEX-vvvv.txt | 3 # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s.
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/X86/ |
D | invalid-VEX-vvvv-32.txt | 3 # Make sure the VEX.vvvv being all 1s check doesn't ignore bit 3 in 32-bit mode.
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D | invalid-VEX-vvvv.txt | 3 # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s.
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/external/llvm/test/MC/Disassembler/X86/ |
D | invalid-VEX-vvvv.txt | 3 # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s.
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/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.c | 1269 insn->vvvv = (Reg)fixupRegValue(insn, in fixupReg() 1271 insn->vvvv, in fixupReg() 1450 insn->vvvv = vvvvFromVEX3of3(insn->vexPrefix[2]); in readVVVV() 1452 insn->vvvv = vvvvFromVEX2of2(insn->vexPrefix[1]); in readVVVV() 1457 insn->vvvv &= 0x7; in readVVVV() 1478 needVVVV = hasVVVV && (insn->vvvv != 0); in readOperands()
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D | X86DisassemblerDecoder.h | 490 Reg vvvv; member
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D | X86Disassembler.cpp | 554 translateRegister(mcInst, insn.vvvv); in translateOperand()
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/external/icu/icu4c/source/data/locales/ |
D | es_AR.txt | 38 Hmsvvvv{"HH:mm:ss (vvvv)"}
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D | es_US.txt | 208 Hmsvvvv{"HH:mm:ss (vvvv)"}
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/external/cldr/tools/java/org/unicode/cldr/util/ |
D | VerifyZones.java | 134 …private final static List<Format> FORMAT_LIST = Arrays.asList(Format.VVVV, Format.vvvv, Format.v, …
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/external/tcpdump/tests/ |
D | TESTLIST | 197 of10_s4810-vvvv of10_s4810.pcap of10_s4810-vvvv.out -vvvv
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