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Searched refs:wrmsrl (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/x86/cpu/
Dmtrr.c32 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN); in mtrr_open()
41 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN); in mtrr_close()
60 wrmsrl(MTRR_PHYS_BASE_MSR(i), req->start | req->type); in mtrr_commit()
61 wrmsrl(MTRR_PHYS_MASK_MSR(i), mask | MTRR_PHYS_MASK_VALID); in mtrr_commit()
66 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); in mtrr_commit()
/external/u-boot/cmd/x86/
Dmtrr.c77 wrmsrl(MTRR_PHYS_BASE_MSR(reg), base); in do_mtrr_set()
78 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); in do_mtrr_set()
95 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); in mtrr_set_valid()
/external/u-boot/arch/x86/include/asm/
Dmsr.h127 #define wrmsrl(msr, val) \ macro
137 wrmsrl(msr, val); in msr_clrsetbits_64()
146 wrmsrl(msr, val); in msr_setbits_64()
155 wrmsrl(msr, val); in msr_clrbits_64()
/external/u-boot/arch/x86/cpu/coreboot/
Dcoreboot.c58 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); in board_final_cleanup()
59 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0); in board_final_cleanup()