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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt40 0x10 0x43 0x23 0x0e
43 0x10 0x43 0x21 0x8e
46 0x10 0x43 0x21 0x0e
49 0x10 0x43 0x21 0xce
52 0x10 0x43 0x21 0x4e
55 0x10 0x43 0x20 0x0e
58 0x10 0x43 0x20 0x8e
61 0x10 0x43 0x20 0x4e
64 0x10 0x43 0x20 0xce
67 0x10 0x40 0x1b 0x4e
[all …]
Dqpx.txt4 0x10 0x60 0x2a 0x10
7 0x10 0x64 0x28 0x2a
13 0x10 0x64 0x2a 0x08
16 0x10 0x64 0x28 0x88
19 0x10 0x60 0x2e 0x9c
25 0x10 0x60 0x2f 0x9c
31 0x10 0x63 0x18 0x08
34 0x10 0x64 0x28 0x10
37 0x10 0x64 0x22 0x88
40 0x10 0x60 0x2e 0x5c
[all …]
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt40 0x10 0x43 0x23 0x0e
43 0x10 0x43 0x21 0x8e
46 0x10 0x43 0x21 0x0e
49 0x10 0x43 0x21 0xce
52 0x10 0x43 0x21 0x4e
55 0x10 0x43 0x20 0x0e
58 0x10 0x43 0x20 0x8e
61 0x10 0x43 0x20 0x4e
64 0x10 0x43 0x20 0xce
67 0x10 0x40 0x1b 0x4e
[all …]
Dqpx.txt4 0x10 0x60 0x2a 0x10
7 0x10 0x64 0x28 0x2a
13 0x10 0x64 0x2a 0x08
16 0x10 0x64 0x28 0x88
19 0x10 0x60 0x2e 0x9c
25 0x10 0x60 0x2f 0x9c
31 0x10 0x63 0x18 0x08
34 0x10 0x64 0x28 0x10
37 0x10 0x64 0x22 0x88
40 0x10 0x60 0x2e 0x5c
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Darm-vmrs_vmsr.txt8 [0x10,0xfa,0xf1,0xee]
9 [0x10,0xfa,0xf1,0xee]
10 [0x10,0xfa,0xf1,0xee]
11 [0x10,0xaa,0xf1,0xee]
12 [0x10,0x2a,0xf0,0xee]
13 [0x10,0x3a,0xf0,0xee]
14 [0x10,0x4a,0xf7,0xee]
15 [0x10,0x5a,0xf6,0xee]
16 [0x10,0x6a,0xf5,0xee]
17 [0x10,0xda,0xf1,0xee]
[all …]
Dthumb-vmrs_vmsr.txt16 [0xf1,0xee,0x10,0xfa]
17 [0xf1,0xee,0x10,0xfa]
18 [0xf1,0xee,0x10,0xfa]
19 [0xf1,0xee,0x10,0xaa]
20 [0xf0,0xee,0x10,0x2a]
21 [0xf0,0xee,0x10,0x3a]
22 [0xf7,0xee,0x10,0x4a]
23 [0xf6,0xee,0x10,0x5a]
24 [0xf5,0xee,0x10,0x6a]
25 [0xf1,0xee,0x10,0xda]
[all …]
Dunpredictable-AI1cmp-arm.txt4 # CHECK: 0x01 0x10 0x50 0x03
5 0x01 0x10 0x50 0x03
8 # CHECK: 0x82 0x10 0x50 0x01
9 0x82 0x10 0x50 0x01
12 # CHECK: 0x02 0x10 0x50 0x01
13 0x02 0x10 0x50 0x01
20 # CHECK: 0x10 0x11 0x52 0x01
21 0x10 0x11 0x52 0x01
24 # CHECK: 0x10 0x0f 0x51 0x01
25 0x10 0x0f 0x51 0x01
[all …]
Dinvalid-thumbv8.txt38 [0x00 0xee 0x10 0x01]
41 # CHECK-NEXT: [0x00 0xee 0x10 0x01]
43 [0x00 0xfe 0x10 0x01]
46 # CHECK-NEXT: [0x00 0xfe 0x10 0x01]
48 [0x00 0xfe 0x10 0x0e]
51 # CHECK-NEXT: [0x00 0xfe 0x10 0x0e]
53 [0x00 0xfe 0x10 0x0f]
56 # CHECK-NEXT: [0x00 0xfe 0x10 0x0f]
58 [0x10 0xee 0x10 0x01]
61 # CHECK-NEXT: [0x10 0xee 0x10 0x01]
[all …]
Dinvalid-armv8.txt38 [0x10 0x01 0x00 0xee]
41 # CHECK-NEXT: [0x10 0x01 0x00 0xee]
43 [0x10 0x01 0x00 0xfe]
46 # CHECK-NEXT: [0x10 0x01 0x00 0xfe]
48 [0x10 0x0e 0x00 0xfe]
51 # CHECK-NEXT: [0x10 0x0e 0x00 0xfe]
53 [0x10 0x0f 0x00 0xfe]
56 # CHECK-NEXT: [0x10 0x0f 0x00 0xfe]
58 [0x10 0x01 0x10 0xee]
61 # CHECK-NEXT: [0x10 0x01 0x10 0xee]
[all …]
/external/bouncycastle/repackaged/bcprov/src/main/java/com/android/org/bouncycastle/crypto/engines/
DRC2Engine.java212 int x76, x54, x32, x10; in encryptBlock() local
217 x10 = ((in[inOff + 1] & 0xff) << 8) + (in[inOff + 0] & 0xff); in encryptBlock()
221 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
222 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
223 x54 = rotateWordLeft(x54 + (x76 & ~x32) + (x10 & x32) + workingKey[i+2], 3); in encryptBlock()
224 x76 = rotateWordLeft(x76 + (x10 & ~x54) + (x32 & x54) + workingKey[i+3], 5); in encryptBlock()
227 x10 += workingKey[x76 & 63]; in encryptBlock()
228 x32 += workingKey[x10 & 63]; in encryptBlock()
234 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
235 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
[all …]
/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/crypto/engines/
DRC2Engine.java210 int x76, x54, x32, x10; in encryptBlock() local
215 x10 = ((in[inOff + 1] & 0xff) << 8) + (in[inOff + 0] & 0xff); in encryptBlock()
219 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
220 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
221 x54 = rotateWordLeft(x54 + (x76 & ~x32) + (x10 & x32) + workingKey[i+2], 3); in encryptBlock()
222 x76 = rotateWordLeft(x76 + (x10 & ~x54) + (x32 & x54) + workingKey[i+3], 5); in encryptBlock()
225 x10 += workingKey[x76 & 63]; in encryptBlock()
226 x32 += workingKey[x10 & 63]; in encryptBlock()
232 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
233 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
[all …]
/external/scapy/test/
Dcan.uts34 …x10\x00\x00\x00\x10\x00\x00\x00\x00\x00\x06B\x08\x7f\x00\x00@\x08\x10\x00\x00\x00\x00\x00\xf8\xf3m…
/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_mode_18_34.s121 mov x10,x2
159 st1 {v0.8b},[x10],x3
160 st1 {v1.8b},[x10],x3
162 st1 {v2.8b},[x10],x3
165 st1 {v3.8b},[x10],x3
168 st1 {v4.8b},[x10],x3
170 st1 {v5.8b},[x10],x3
172 st1 {v6.8b},[x10],x3
174 st1 {v7.8b},[x10],x3
177 sub x20,x10,x14
[all …]
Dihevc_sao_edge_offset_class1.s85 ADD x10,x0,x9 //pu1_src[row * src_strd + wd - 1]
89 LDRB w14,[x10] //Load pu1_src[row * src_strd + wd - 1]
90 ADD x10,x10,x1
129 MOV x10,x0 //*pu1_src
144 ADD x10,x10,x1 //*pu1_src + src_strd
145 LD1 {v18.16b},[x10] //pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
146 ADD x6,x10,x1 //II Iteration *pu1_src + src_strd
152 SUB x10,x10,x1
209 ST1 { v20.16b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
215 ST1 { v30.16b},[x10],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
[all …]
Dihevc_intra_pred_luma_mode_27_to_33.s159 add x10,x8,x9 //(i row)*pu1_ref[ref_main_idx]
162 ld1 {v23.8b},[x10],x11 //(i row)ref_main_idx
166 ld1 {v9.8b},[x10] //(i row)ref_main_idx_1
171 add x10,x8,x9 //(iii)*pu1_ref[ref_main_idx]
188 ld1 {v16.8b},[x10],x11 //(iii)ref_main_idx
191 ld1 {v17.8b},[x10] //(iii)ref_main_idx_1
211 add x10,x8,x9 //(v)*pu1_ref[ref_main_idx]
213 ld1 {v23.8b},[x10],x11 //(v)ref_main_idx
220 ld1 {v9.8b},[x10] //(v)ref_main_idx_1
232 add x10,x8,x9 //(vii)*pu1_ref[ref_main_idx]
[all …]
Dihevc_intra_pred_chroma_mode_27_to_33.s154 add x10,x8,x9 //(i row)*pu1_ref[ref_main_idx]
157 ld1 {v23.8b},[x10],x11 //(i row)ref_main_idx
161 ld1 {v9.8b},[x10] //(i row)ref_main_idx_1
166 add x10,x8,x9 //(iii)*pu1_ref[ref_main_idx]
183 ld1 {v16.8b},[x10],x11 //(iii)ref_main_idx
186 ld1 {v17.8b},[x10] //(iii)ref_main_idx_1
206 add x10,x8,x9 //(v)*pu1_ref[ref_main_idx]
208 ld1 {v23.8b},[x10],x11 //(v)ref_main_idx
215 ld1 {v9.8b},[x10] //(v)ref_main_idx_1
227 add x10,x8,x9 //(vii)*pu1_ref[ref_main_idx]
[all …]
Dihevc_inter_pred_luma_copy.s103 add x10,x1,x3 //pu1_dst_tmp += dst_strd
107 st1 {v0.s}[0],[x10],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
110 st1 {v0.s}[0],[x10],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
113 st1 {v0.s}[0],[x10],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
120 sub x1,x10,x15 //pu1_dst = pu1_dst_tmp
141 add x10,x1,x3 //pu1_dst_tmp += dst_strd
144 st1 {v1.8b},[x10],x3 //vst1_u8(pu1_dst_tmp, tmp_src)
147 st1 {v2.8b},[x10],x3 //vst1_u8(pu1_dst_tmp, tmp_src)
149 st1 {v3.8b},[x10],x3 //vst1_u8(pu1_dst_tmp, tmp_src)
155 sub x1,x10,x15 //pu1_dst = pu1_dst_tmp
[all …]
/external/u-boot/arch/arm/lib/
Dgic_64.S82 mrs x10, mpidr_el1
83 lsr x9, x10, #32
84 bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
103 add x10, x9, #(1 << 16) /* SGI_Base */
105 str w11, [x10, GICR_IGROUPRn]
106 str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
108 str w11, [x10, GICR_ISENABLERn]
111 mrs x10, ICC_SRE_EL3
112 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
114 msr ICC_SRE_EL3, x10
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dunpredictable-AI1cmp-arm.txt4 # CHECK: 0x01 0x10 0x50 0x03
5 0x01 0x10 0x50 0x03
8 # CHECK: 0x82 0x10 0x50 0x01
9 0x82 0x10 0x50 0x01
12 # CHECK: 0x02 0x10 0x50 0x01
13 0x02 0x10 0x50 0x01
20 # CHECK: 0x10 0x11 0x52 0x01
21 0x10 0x11 0x52 0x01
24 # CHECK: 0x10 0x0f 0x51 0x01
25 0x10 0x0f 0x51 0x01
[all …]
Dinvalid-armv8.txt38 [0x10 0x01 0x00 0xee]
41 # CHECK-NEXT: [0x10 0x01 0x00 0xee]
43 [0x10 0x01 0x00 0xfe]
46 # CHECK-NEXT: [0x10 0x01 0x00 0xfe]
48 [0x10 0x0e 0x00 0xfe]
51 # CHECK-NEXT: [0x10 0x0e 0x00 0xfe]
53 [0x10 0x0f 0x00 0xfe]
56 # CHECK-NEXT: [0x10 0x0f 0x00 0xfe]
58 [0x10 0x01 0x10 0xee]
61 # CHECK-NEXT: [0x10 0x01 0x10 0xee]
[all …]
Dinvalid-thumbv8.txt38 [0x00 0xee 0x10 0x01]
41 # CHECK-NEXT: [0x00 0xee 0x10 0x01]
43 [0x00 0xfe 0x10 0x01]
46 # CHECK-NEXT: [0x00 0xfe 0x10 0x01]
48 [0x00 0xfe 0x10 0x0e]
51 # CHECK-NEXT: [0x00 0xfe 0x10 0x0e]
53 [0x00 0xfe 0x10 0x0f]
56 # CHECK-NEXT: [0x00 0xfe 0x10 0x0f]
58 [0x10 0xee 0x10 0x01]
61 # CHECK-NEXT: [0x10 0xee 0x10 0x01]
[all …]
/external/libaom/libaom/av1/encoder/x86/
Dav1_fwd_txfm1d_sse4.c1214 __m128i x10[64]; in av1_fdct64_new_sse4_1() local
1215 x10[0] = x9[0]; in av1_fdct64_new_sse4_1()
1216 x10[1] = x9[1]; in av1_fdct64_new_sse4_1()
1217 x10[2] = x9[2]; in av1_fdct64_new_sse4_1()
1218 x10[3] = x9[3]; in av1_fdct64_new_sse4_1()
1219 x10[4] = x9[4]; in av1_fdct64_new_sse4_1()
1220 x10[5] = x9[5]; in av1_fdct64_new_sse4_1()
1221 x10[6] = x9[6]; in av1_fdct64_new_sse4_1()
1222 x10[7] = x9[7]; in av1_fdct64_new_sse4_1()
1223 x10[8] = x9[8]; in av1_fdct64_new_sse4_1()
[all …]
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-icmp.ll655 ; MIPS32: sll [[T8]],[[T8]],0x10
656 ; MIPS32: sll [[T9]],[[T9]],0x10
660 ; MIPS32: srl [[T4]],[[T4]],0x10
661 ; MIPS32: sll [[T4]],[[T4]],0x10
663 ; MIPS32: srl [[T10:.*]],a0,0x10
664 ; MIPS32: srl [[T0]],[[T0]],0x10
665 ; MIPS32: sll [[T10]],[[T10]],0x10
666 ; MIPS32: sll [[T0]],[[T0]],0x10
669 ; MIPS32: sll [[T10]],[[T10]],0x10
670 ; MIPS32: sll [[T8]],[[T8]],0x10
[all …]
Dvector-cast.ll58 ; MIPS32: srl t2,t2,0x10
64 ; MIPS32: sll t2,t2,0x10
99 ; MIPS32: srl v0,v0,0x10
105 ; MIPS32: sll v0,v0,0x10
140 ; MIPS32: srl v0,v0,0x10
146 ; MIPS32: sll v0,v0,0x10
181 ; MIPS32: srl v0,v0,0x10
187 ; MIPS32: sll v0,v0,0x10
222 ; MIPS32: srl v0,v0,0x10
223 ; MIPS32: sll v0,v0,0x10
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32/
Dvalid-fp64-el.txt8 0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4
9 0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4
10 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
11 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
12 0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
13 0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
14 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
15 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
16 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
17 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2

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