/external/tcpdump/tests/ |
D | telnet-iac-check-oobr.out | 2 …x18 0x1 SE, SB 0x7b 0xf5 0 0 0x1 0x1 0x8 0xa 0x7 0x1d 0xa8 0xd4 0x59 0x3c 0x88 0xa8 0xff 0xfe 0x24…
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/MBlaze/ |
D | mblaze_typea.txt | 8 0x00 0x22 0x18 0x00 11 0x08 0x22 0x18 0x00 14 0x10 0x22 0x18 0x00 17 0x18 0x22 0x18 0x00 20 0x84 0x22 0x18 0x00 23 0x8c 0x22 0x18 0x00 26 0x14 0x22 0x18 0x01 29 0x14 0x22 0x18 0x03 32 0x48 0x22 0x18 0x00 35 0x48 0x22 0x18 0x02 [all …]
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D | mblaze_branch.txt | 8 0x9c 0x02 0x18 0x00 11 0x9c 0xa2 0x18 0x00 14 0x9c 0x82 0x18 0x00 17 0x9c 0x62 0x18 0x00 20 0x9c 0x42 0x18 0x00 23 0x9c 0x22 0x18 0x00 26 0x9e 0x02 0x18 0x00 29 0x9e 0xa2 0x18 0x00 32 0x9e 0x82 0x18 0x00 35 0x9e 0x62 0x18 0x00 [all …]
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/external/python/cpython2/Demo/tix/bitmaps/ |
D | bold.xbm | 4 0x00, 0x00, 0x00, 0x00, 0xfc, 0x07, 0xfc, 0x0f, 0x18, 0x1c, 0x18, 0x18, 5 0x18, 0x18, 0x18, 0x1c, 0xf8, 0x0f, 0xf8, 0x0f, 0x18, 0x18, 0x18, 0x30, 6 0x18, 0x30, 0x18, 0x38, 0xfc, 0x3f, 0xfc, 0x1f};
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/external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
D | valid-mips32r6-el.txt | 28 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260 29 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20 30 0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1336 31 0xfa 0xff 0x42 0x18 # CHECK: bgezalc $2, -20 46 0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1336 47 0xfa 0xff 0x02 0x18 # CHECK: blezalc $2, -20 58 0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4 59 0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4 60 0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4 61 0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4 [all …]
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D | valid-mips32r6.txt | 39 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336 40 0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20 42 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336 43 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20 44 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260 45 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20 92 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 93 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 103 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 104 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r6/ |
D | valid-mips32r6-el.txt | 29 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260 30 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20 31 0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1336 32 0xfa 0xff 0x42 0x18 # CHECK: bgezalc $2, -20 47 0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1336 48 0xfa 0xff 0x02 0x18 # CHECK: blezalc $2, -20 59 0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4 60 0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4 61 0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4 62 0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4 [all …]
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D | valid-mips32r6.txt | 41 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336 42 0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20 44 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336 45 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20 46 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260 47 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20 98 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 99 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 109 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 110 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 [all …]
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/external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
D | valid-mips64r6-el.txt | 26 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260 27 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20 28 0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1336 29 0xfa 0xff 0x42 0x18 # CHECK: bgezalc $2, -20 37 0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1336 38 0xfa 0xff 0x02 0x18 # CHECK: blezalc $2, -20 65 0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4 66 0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4 67 0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4 68 0x82 0x18 0x84 0x46 # CHECK: cmp.eq.s $f2, $f3, $f4 [all …]
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D | valid-mips64r6.txt | 56 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336 57 0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20 59 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336 60 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20 61 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260 62 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20 111 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 112 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 122 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 123 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r6/ |
D | valid-mips64r6-el.txt | 26 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260 27 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20 28 0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1336 29 0xfa 0xff 0x42 0x18 # CHECK: bgezalc $2, -20 37 0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1336 38 0xfa 0xff 0x02 0x18 # CHECK: blezalc $2, -20 65 0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4 66 0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4 67 0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4 68 0x82 0x18 0x84 0x46 # CHECK: cmp.eq.s $f2, $f3, $f4 [all …]
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D | valid-mips64r6.txt | 58 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336 59 0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20 61 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336 62 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20 63 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260 64 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20 117 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 118 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 128 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 129 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 [all …]
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/external/llvm/test/MC/Disassembler/PowerPC/ |
D | ppc64-encoding-fp.txt | 61 0xfc 0x40 0x18 0x90 64 0xfc 0x40 0x18 0x91 67 0xfc 0x40 0x18 0x50 70 0xfc 0x40 0x18 0x51 139 0xfc 0x40 0x18 0x2c 142 0xfc 0x40 0x18 0x2d 145 0xec 0x40 0x18 0x2c 148 0xec 0x40 0x18 0x2d 151 0xfc 0x40 0x18 0x30 154 0xfc 0x40 0x18 0x31 [all …]
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/external/u-boot/arch/arm/lib/ |
D | crt0_64.S | 86 mov x18, x0 98 ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */ 100 ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */ 111 ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */ 113 ldr x0, [x18, #GD_RELOCADDR] /* x0 <- gd->relocaddr */ 127 csel x18, x0, x18, ne 150 mov x0, x18 /* gd_t */ 151 ldr x1, [x18, #GD_RELOCADDR] /* dest_addr */
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
D | ppc64-encoding-fp.txt | 61 0xfc 0x40 0x18 0x90 64 0xfc 0x40 0x18 0x91 67 0xfc 0x40 0x18 0x50 70 0xfc 0x40 0x18 0x51 139 0xfc 0x40 0x18 0x2c 142 0xfc 0x40 0x18 0x2d 145 0xec 0x40 0x18 0x2c 148 0xec 0x40 0x18 0x2d 151 0xfc 0x40 0x18 0x30 154 0xfc 0x40 0x18 0x31 [all …]
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | gicv3-regs.txt | 116 0x3b 0xcc 0x18 0xd5 118 0x25 0xc8 0x18 0xd5 120 0x2d 0xcb 0x18 0xd5 122 0xb5 0xcb 0x18 0xd5 124 0xd9 0xcb 0x18 0xd5 126 0xfc 0xcb 0x18 0xd5 128 0x67 0xcc 0x18 0xd5 130 0x69 0xc8 0x18 0xd5 132 0x1d 0x46 0x18 0xd5 134 0x98 0xcc 0x18 0xd5 [all …]
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D | armv8.2a-statistical-profiling.txt | 8 [0x00,0x9a,0x18,0xd5] 9 [0x20,0x9a,0x18,0xd5] 10 [0x60,0x9a,0x18,0xd5] 11 [0xe0,0x9a,0x18,0xd5] 14 [0x00,0x99,0x18,0xd5] 15 [0x40,0x99,0x18,0xd5] 16 [0x60,0x99,0x18,0xd5] 17 [0x80,0x99,0x18,0xd5] 18 [0xa0,0x99,0x18,0xd5] 19 [0xc0,0x99,0x18,0xd5] [all …]
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D | ras-extension.txt | 15 [0x20,0x53,0x18,0xd5] 16 [0x20,0x54,0x18,0xd5] 17 [0x40,0x54,0x18,0xd5] 18 [0x60,0x54,0x18,0xd5] 19 [0x00,0x55,0x18,0xd5] 20 [0x20,0x55,0x18,0xd5] 21 [0x20,0xc1,0x18,0xd5]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
D | gicv3-regs.txt | 116 0x3b 0xcc 0x18 0xd5 118 0x25 0xc8 0x18 0xd5 120 0x2d 0xcb 0x18 0xd5 122 0xb5 0xcb 0x18 0xd5 124 0xd9 0xcb 0x18 0xd5 126 0xfc 0xcb 0x18 0xd5 128 0x67 0xcc 0x18 0xd5 130 0x69 0xc8 0x18 0xd5 132 0x1d 0x46 0x18 0xd5 134 0x98 0xcc 0x18 0xd5 [all …]
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D | armv8.2a-statistical-profiling.txt | 8 [0x00,0x9a,0x18,0xd5] 9 [0x20,0x9a,0x18,0xd5] 10 [0x60,0x9a,0x18,0xd5] 11 [0xe0,0x9a,0x18,0xd5] 14 [0x00,0x99,0x18,0xd5] 15 [0x40,0x99,0x18,0xd5] 16 [0x60,0x99,0x18,0xd5] 17 [0x80,0x99,0x18,0xd5] 18 [0xa0,0x99,0x18,0xd5] 19 [0xc0,0x99,0x18,0xd5] [all …]
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D | ras-extension.txt | 15 [0x20,0x53,0x18,0xd5] 16 [0x20,0x54,0x18,0xd5] 17 [0x40,0x54,0x18,0xd5] 18 [0x60,0x54,0x18,0xd5] 19 [0x00,0x55,0x18,0xd5] 20 [0x20,0x55,0x18,0xd5] 21 [0x20,0xc1,0x18,0xd5]
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/external/syzkaller/sys/test/test/ |
D | align0 | 1 …00200000003000400000000000500000000000000", 0x18, &(0x7f0000001000)=@align0={0x1, 0x2, 0x3, 0x4, 0… 2 syz_compare(&(0x7f0000000000)="", 0x18, &(0x7f0000001000)=@align0={}, 0x17) # EBADF 3 syz_compare(&(0x7f0000000000)="", 0x18, &(0x7f0000001000)=@align0={0x1}, 0x18) # EINVAL
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-platform-reg.ll | 1 ; RUN: llc -mtriple=arm64-apple-ios -mattr=+reserve-x18 -o - %s | FileCheck %s --check-prefix=CHECK… 2 ; RUN: llc -mtriple=arm64-freebsd-gnu -mattr=+reserve-x18 -o - %s | FileCheck %s --check-prefix=CHE… 5 ; x18 is reserved as a platform register on Darwin but not on other 17 ; CHECK: ldr x18 18 ; CHECK: str x18 21 ; CHECK-RESERVE-X18-NOT: ldr x18 24 ; CHECK-RESERVE-X18-NOT: ldr x18
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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
D | vector-icmp.ll | 2715 ; MIPS32: sll [[T8]],[[T8]],0x18 2716 ; MIPS32: sll [[T9]],[[T9]],0x18 2729 ; MIPS32: sll [[T4]],[[T4]],0x18 2730 ; MIPS32: sll [[T9]],[[T9]],0x18 2745 ; MIPS32: sll [[T8]],[[T8]],0x18 2746 ; MIPS32: sll [[T9]],[[T9]],0x18 2755 ; MIPS32: srl [[T10:.*]],a0,0x18 2756 ; MIPS32: srl [[T0]],[[T0]],0x18 2757 ; MIPS32: sll [[T10]],[[T10]],0x18 2758 ; MIPS32: sll [[T0]],[[T0]],0x18 [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | arm64-platform-reg.ll | 1 ; RUN: llc -mtriple=arm64-apple-ios -mattr=+reserve-x18 -o - %s | FileCheck %s --check-prefix=CHECK… 2 ; RUN: llc -mtriple=arm64-freebsd-gnu -mattr=+reserve-x18 -o - %s | FileCheck %s --check-prefix=CHE… 4 ; RUN: llc -mtriple=aarch64-fuchsia -mattr=+reserve-x18,+reserve-x20 -o - %s | FileCheck %s --check… 9 ; x18 is reserved as a platform register on Darwin but not on other 21 ; CHECK: ldr x18 22 ; CHECK: str x18 25 ; CHECK-RESERVE-X18-NOT: ldr x18 29 ; CHECK-RESERVE-X18-NOT: ldr x18
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