| /external/tcpdump/tests/ |
| D | telnet-iac-check-oobr.out | 2 …x24 0xff 0xfa 0x18 0x1 SE, SB 0x7b 0xf5 0 0 0x1 0x1 0x8 0xa 0x7 0x1d 0xa8 0xd4 0x59 0x3c 0x88 0xa8…
|
| /external/python/cpython2/Demo/tix/bitmaps/ |
| D | filebox.xbm | 6 0xe4, 0xff, 0xff, 0x27, 0x24, 0x00, 0x00, 0x24, 0x24, 0x00, 0x00, 0x24,
8 0x24, 0x50, 0x02, 0x25, 0x24, 0x40, 0x02, 0x24, 0x24, 0x50, 0x02, 0x25,
9 0x24, 0x40, 0x02, 0x24, 0x24, 0x50, 0x02, 0x25, 0x24, 0x40, 0x02, 0x24,
10 0x24, 0x50, 0x02, 0x25, 0xe4, 0x7f, 0xfe, 0x27, 0x04, 0x00, 0x00, 0x20,
11 0xe4, 0xff, 0xff, 0x27, 0x24, 0x00, 0x00, 0x24, 0x24, 0x00, 0x00, 0x24,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | fma.ll | 15 ; FMA32-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xc5,0xfa,0x10,0x44,0x24,0x08]
17 ; FMA32-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x0c]
19 …XT: vfmadd213ss {{[0-9]+}}(%esp), %xmm0, %xmm1 ## encoding: [0xc4,0xe2,0x79,0xa9,0x4c,0x24,0x10]
21 ; FMA32-NEXT: vmovss %xmm1, (%esp) ## encoding: [0xc5,0xfa,0x11,0x0c,0x24]
22 ; FMA32-NEXT: flds (%esp) ## encoding: [0xd9,0x04,0x24]
64 ; FMA32-NEXT: vmovsd {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xc5,0xfb,0x10,0x44,0x24,0x10]
66 ; FMA32-NEXT: vmovsd {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfb,0x10,0x4c,0x24,0x18]
68 …XT: vfmadd213sd {{[0-9]+}}(%esp), %xmm0, %xmm1 ## encoding: [0xc4,0xe2,0xf9,0xa9,0x4c,0x24,0x20]
70 ; FMA32-NEXT: vmovsd %xmm1, (%esp) ## encoding: [0xc5,0xfb,0x11,0x0c,0x24]
71 ; FMA32-NEXT: fldl (%esp) ## encoding: [0xdd,0x04,0x24]
[all …]
|
| D | x86-interrupt_cc.ll | 33 ; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xbc,0x24,0x2e,0x08,0x00,0x00]
35 ; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xb4,0x24,0x2c,0x08,0x00,0x00]
37 ; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xac,0x24,0x2a,0x08,0x00,0x00]
39 ; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0xa4,0x24,0x28,0x08,0x00,0x00]
41 ; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x9c,0x24,0x26,0x08,0x00,0x00]
43 ; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x94,0x24,0x24,0x08,0x00,0x00]
45 ; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x8c,0x24,0x22,0x08,0x00,0x00]
47 ; CHECK64-KNL-NEXT: ## encoding: [0xc5,0xf8,0x91,0x84,0x24,0x20,0x08,0x00,0x00]
49 ; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x7c,0x24,0x1f]
51 ; CHECK64-KNL-NEXT: ## encoding: [0x62,0x61,0x7c,0x48,0x11,0x74,0x24,0x1e]
[all …]
|
| /external/boringssl/linux-aarch64/crypto/fipsmodule/ |
| D | sha512-armv8.S | 71 stp x23,x24,[sp,#48]
78 ldp x24,x25,[x0,#4*8]
93 ror x16,x24,#14
95 eor x6,x24,x24,ror#23
96 and x17,x25,x24
97 bic x19,x26,x24
121 and x17,x24,x23
146 bic x19,x24,x22
168 add x24,x24,x28 // h+=K[i]
172 add x24,x24,x6 // h+=X[i]
[all …]
|
| D | armv8-mont.S | 31 stp x23,x24,[sp,#48]
217 ldp x23,x24,[x29,#48]
231 stp x23,x24,[sp,#48]
269 mov x24,xzr
319 adcs x24,x24,x14
333 adcs x24,x24,x16
346 adcs x24,x24,x14
358 adcs x24,x24,x15
369 adds x24,x24,x16
379 stp x23,x24,[x2],#8*2 // t[4..5]
[all …]
|
| /external/boringssl/ios-aarch64/crypto/fipsmodule/ |
| D | sha512-armv8.S | 70 stp x23,x24,[sp,#48]
77 ldp x24,x25,[x0,#4*8]
92 ror x16,x24,#14
94 eor x6,x24,x24,ror#23
95 and x17,x25,x24
96 bic x19,x26,x24
120 and x17,x24,x23
145 bic x19,x24,x22
167 add x24,x24,x28 // h+=K[i]
171 add x24,x24,x6 // h+=X[i]
[all …]
|
| D | armv8-mont.S | 30 stp x23,x24,[sp,#48]
216 ldp x23,x24,[x29,#48]
230 stp x23,x24,[sp,#48]
268 mov x24,xzr
318 adcs x24,x24,x14
332 adcs x24,x24,x16
345 adcs x24,x24,x14
357 adcs x24,x24,x15
368 adds x24,x24,x16
378 stp x23,x24,[x2],#8*2 // t[4..5]
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 175 0x10 0x43 0x24 0x0c
181 0x10 0x43 0x24 0x4c
241 0x10 0x43 0x24 0x00
244 0x10 0x43 0x24 0x40
247 0x10 0x43 0x24 0x80
250 0x10 0x43 0x24 0xc0
364 0x10 0x43 0x24 0x02
367 0x10 0x43 0x24 0x42
370 0x10 0x43 0x24 0x82
424 0x10 0x43 0x24 0x06
[all …]
|
| D | ppc64-encoding-bookIII.txt | 4 0x4c 0x00 0x02 0x24
10 0x7c 0x80 0x01 0x24
13 0x7c 0x81 0x01 0x24
94 0x7c 0x80 0x2b 0x24
109 0x7c 0x00 0x22 0x24
134 0x7c 0x0b 0x66 0x24
136 0x7c 0x0b 0x67 0x24
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32/ |
| D | valid-fp64-el.txt | 8 0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4
9 0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4
10 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
11 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
14 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
|
| D | valid-fp64.txt | 8 0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4
9 0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4
10 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
11 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
14 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 175 0x10 0x43 0x24 0x0c
181 0x10 0x43 0x24 0x4c
241 0x10 0x43 0x24 0x00
244 0x10 0x43 0x24 0x40
247 0x10 0x43 0x24 0x80
250 0x10 0x43 0x24 0xc0
364 0x10 0x43 0x24 0x02
367 0x10 0x43 0x24 0x42
370 0x10 0x43 0x24 0x82
424 0x10 0x43 0x24 0x06
[all …]
|
| D | ppc64-encoding-bookIII.txt | 4 0x7c 0x80 0x01 0x24
7 0x7c 0x81 0x01 0x24
88 0x7c 0x80 0x2b 0x24
100 0x7c 0x00 0x22 0x24
125 0x7c 0x0b 0x66 0x24
127 0x7c 0x0b 0x67 0x24
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-fp64.txt | 8 0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4
9 0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4
10 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
11 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
14 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
|
| D | valid-fp64-el.txt | 8 0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4
9 0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4
10 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
11 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
14 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-fp64.txt | 8 0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4
9 0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4
10 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
11 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
14 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
|
| D | valid-fp64-el.txt | 8 0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4
9 0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4
10 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
11 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
14 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-fp64.txt | 8 0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4
9 0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4
10 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
11 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
14 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
|
| D | valid-fp64-el.txt | 8 0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4
9 0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4
10 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
11 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
14 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | ilp32-diagnostics.s | 78 ldr x24, [x23, #:got_lo12:sym]
82 ldr x24, [x23, :gottprel_lo12:sym]
91 ldr x24, [x23, #:got_lo12:sym]
95 ldr x24, [x23, :gottprel_lo12:sym]
|
| D | trace-regs.s | 18 mrs x24, trcoslsr
47 mrs x24, trcsyncpr
77 mrs x24, trcimspec0
78 mrs x24, trcimspec1
97 mrs x24, trcrsctlr14
147 mrs x24, trcacvr7
150 mrs x24, trcacvr10
189 mrs x24, trccidcvr1
190 mrs x24, trccidcvr2
424 msr trcconfigr, x24
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-register-pairing.ll | 14 ; CHECK: stp x24, x23, [sp, #96]
20 ; CHECK: ldp x24, x23, [sp, #96]
52 ; CHECK: stp x24, x23, [sp, #96]
58 ; CHECK: ldp x24, x23, [sp, #96]
70 ; CHECK-NOTMACHO: stp x26, x24, [sp, #48]
74 ; CHECK-NOTMACHO: ldp x26, x24, [sp, #48]
78 …call void asm sideeffect "mov x0, #42", "~{x0},~{x20},~{x22},~{x24},~{x26},~{x28},~{d9},~{d11},~{d…
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-register-pairing.ll | 14 ; CHECK: stp x24, x23, [sp, #96]
20 ; CHECK: ldp x24, x23, [sp, #96]
52 ; CHECK: stp x24, x23, [sp, #96]
58 ; CHECK: ldp x24, x23, [sp, #96]
70 ; CHECK-NOTMACHO: stp x26, x24, [sp, #48]
74 ; CHECK-NOTMACHO: ldp x26, x24, [sp, #48]
78 …call void asm sideeffect "mov x0, #42", "~{x0},~{x20},~{x22},~{x24},~{x26},~{x28},~{d9},~{d11},~{d…
|
| /external/capstone/suite/MC/AArch64/ |
| D | trace-regs.s.cs | 17 0x98,0x11,0x31,0xd5 = mrs x24, trcoslsr
46 0x18,0x0d,0x31,0xd5 = mrs x24, trcsyncpr
76 0xf8,0x00,0x31,0xd5 = mrs x24, trcimspec0
77 0xf8,0x01,0x31,0xd5 = mrs x24, trcimspec1
96 0x18,0x1e,0x31,0xd5 = mrs x24, trcrsctlr14
146 0x18,0x2e,0x31,0xd5 = mrs x24, trcacvr7
149 0x38,0x24,0x31,0xd5 = mrs x24, trcacvr10
188 0x18,0x32,0x31,0xd5 = mrs x24, trccidcvr1
189 0x18,0x34,0x31,0xd5 = mrs x24, trccidcvr2
214 0x18,0x04,0x11,0xd5 = msr trcconfigr, x24
[all …]
|