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/external/u-boot/arch/arm/dts/
Dimx53-cx9020.dts133 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
134 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
135 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
136 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
137 MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
138 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
139 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
140 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
141 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
142 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
[all …]
/external/libhevc/common/arm64/
Dihevc_intra_pred_chroma_ver.s105 lsl x5, x4, #2 //4nt
113 add x5, x5, #2 //2nt+2
114 add x6, x0, x5 //&src[2nt+1]
116 add x5, x2, x3 //pu1_dst + dst_strd
118 add x8, x5, x3
128 st2 {v20.8b, v21.8b}, [x5],#16
133 st2 {v22.8b, v23.8b}, [x5], x11
141 st2 {v20.8b, v21.8b}, [x5],#16
146 st2 {v22.8b, v23.8b}, [x5], x11
154 st2 {v20.8b, v21.8b}, [x5],#16
[all …]
Dihevc_sao_edge_offset_class2.s73 MOV x5,x7 //Loads pu1_avail
94 MOV x23,x5 //Store pu1_avail in sp
114 LDRB w10,[x5,#4] //pu1_avail[4]
154 LDRB w14,[x5,#7] //pu1_avail[7]
203 LDRB w11,[x5,#3] //pu1_avail[3]
209 LDRB w5,[x5,#2] //pu1_avail[2]
214 CMP x5,#0
241 MOV x5,x23 //Loads pu1_avail
243 LDRb w20, [x5] //pu1_avail[0]
251 LDRB w8,[x5,#1] //pu1_avail[1]
[all …]
Dihevc_sao_edge_offset_class3.s82 MOV x20,x5 //Store pu1_src_top_right in sp
85 MOV x5,x7 //Loads pu1_avail
114 LDRB w9,[x5,#5] //pu1_avail[5]
159 LDRB w10,[x5,#6] //pu1_avail[6]
214 LDRB w11,[x5,#3] //pu1_avail[3]
221 LDRB w5,[x5,#2] //pu1_avail[2]
223 CMP x5,#0
250 MOV x5,x23 //Loads pu1_avail
252 LDRb w20, [x5] //pu1_avail[0]
260 LDRB w8,[x5,#1] //pu1_avail[1]
[all …]
Dihevc_padding.s115 add x5,x4,x1
123 add x6,x5,x1
125 st1 {v2.16b},[x5],#16 //128/8 = 16 bytes store
126 st1 {v2.16b},[x5],#16 //128/8 = 16 bytes store
127 st1 {v2.16b},[x5],#16 //128/8 = 16 bytes store
128 st1 {v2.16b},[x5],#16 //128/8 = 16 bytes store
129 st1 {v2.16b},[x5] //128/8 = 16 bytes store
233 add x5,x4,x1
241 add x6,x5,x1
243 st1 {v2.16b},[x5],#16 //128/8 = 16 bytes store
[all …]
Dihevc_inter_pred_chroma_copy_w16out.s111 mov x16,x5 // ht
141 add x5,x0,x2 //pu1_src +src_strd
146 ld1 {v22.8b},[x5],x2 //vld1_u8(pu1_src_tmp)
151 ld1 {v24.8b},[x5],x2 //vld1_u8(pu1_src_tmp)
156 ld1 {v26.8b},[x5],x2 //vld1_u8(pu1_src_tmp)
165 sub x0,x5,x11
185 add x5,x0,x2 //pu1_src +src_strd
190 ld1 {v22.8b},[x5],x2 //vld1_u8(pu1_src_tmp)
195 ld1 {v24.8b},[x5],x2 //vld1_u8(pu1_src_tmp)
205 lsl x5, x3,#1
[all …]
Dihevc_intra_pred_luma_mode2.s143 lsl x5, x3, #2
163 st1 {v16.8b},[x6],x5
164 st1 {v17.8b},[x7],x5
167 st1 {v18.8b},[x9],x5
171 st1 {v19.8b},[x14],x5
172 st1 {v20.8b},[x6],x5
175 st1 {v21.8b},[x7],x5
176 st1 {v22.8b},[x9],x5
180 st1 {v23.8b},[x14],x5
232 st1 {v16.8b},[x6],x5
[all …]
Dihevc_inter_pred_luma_copy_w16out.s91 mov x16,x5 // ht
110 add x5,x0,x2 //pu1_src +src_strd
115 ld1 {v22.8b},[x5],x2 //vld1_u8(pu1_src_tmp)
120 ld1 {v24.8b},[x5],x2 //vld1_u8(pu1_src_tmp)
125 ld1 {v26.8b},[x5],x2 //vld1_u8(pu1_src_tmp)
134 sub x0,x5,x11
148 lsl x5, x3,#1
149 adds x5, x5,#0
161 add x10,x1,x5
198 st1 {v2.8h},[x10],x5 //vst1q_s16(pi2_dst_tmp, tmp)
[all …]
Dihevc_intra_pred_luma_vert.s107 lsl x5, x4, #1 //2nt
113 add x5, x5, #1 //2nt+1
114 add x6, x0, x5 //&src[2nt+1]
117 add x5, x2, x3
119 add x8, x5, x3
127 st1 {v20.8b, v21.8b}, [x5],#16
132 st1 {v22.8b, v23.8b}, [x5], x11
140 st1 {v20.8b, v21.8b}, [x5],#16
145 st1 {v22.8b, v23.8b}, [x5], x11
152 st1 {v20.8b, v21.8b}, [x5],#16
[all …]
Dihevc_intra_pred_luma_mode_27_to_33.s114 add x8,x6,x5,lsl #2 //*gai4_ihevc_ang_table[mode]
140 mov x5,x4
328 csel x4, x5, x4,le //reload nt
420 sub x20,x12,x5
456 add x5,x8,#1 //row + 1
457 mul x5, x5, x9 //pos = ((row + 1) * intra_pred_ang)
458 and x5,x5,#31 //fract = pos & (31)
459 cmp x14,x5 //if(fract_prev > fract)
464 sub x20,x5,#32
471 mov x14,x5 //fract_prev = fract
[all …]
Dihevc_intra_pred_chroma_mode_27_to_33.s109 add x8,x6,x5,lsl #2 //*gai4_ihevc_ang_table[mode]
135 mov x5,x4
322 csel x4, x5, x4,le //reload nt
414 sub x20,x12,x5
451 add x5,x8,#1 //row + 1
452 mul x5, x5, x9 //pos = ((row + 1) * intra_pred_ang)
453 and x5,x5,#31 //fract = pos & (31)
454 cmp x14,x5 //if(fract_prev > fract)
459 sub x20,x5,#32
466 mov x14,x5 //fract_prev = fract
[all …]
/external/libaom/libaom/av1/encoder/x86/
Dav1_fwd_txfm_sse2.c312 __m128i x5[16]; in fdct8x16_new_sse2() local
313 x5[0] = x4[0]; in fdct8x16_new_sse2()
314 x5[1] = x4[1]; in fdct8x16_new_sse2()
315 x5[2] = x4[2]; in fdct8x16_new_sse2()
316 x5[3] = x4[3]; in fdct8x16_new_sse2()
317 btf_16_sse2(cospi_p56_p08, cospi_m08_p56, x4[4], x4[7], x5[4], x5[7]); in fdct8x16_new_sse2()
318 btf_16_sse2(cospi_p24_p40, cospi_m40_p24, x4[5], x4[6], x5[5], x5[6]); in fdct8x16_new_sse2()
319 x5[8] = _mm_adds_epi16(x4[8], x4[9]); in fdct8x16_new_sse2()
320 x5[9] = _mm_subs_epi16(x4[8], x4[9]); in fdct8x16_new_sse2()
321 x5[10] = _mm_subs_epi16(x4[11], x4[10]); in fdct8x16_new_sse2()
[all …]
Dav1_fwd_txfm1d_sse4.c879 __m128i x5[64]; in av1_fdct64_new_sse4_1() local
880 x5[0] = _mm_add_epi32(x4[0], x4[3]); in av1_fdct64_new_sse4_1()
881 x5[3] = _mm_sub_epi32(x4[0], x4[3]); in av1_fdct64_new_sse4_1()
882 x5[1] = _mm_add_epi32(x4[1], x4[2]); in av1_fdct64_new_sse4_1()
883 x5[2] = _mm_sub_epi32(x4[1], x4[2]); in av1_fdct64_new_sse4_1()
884 x5[4] = x4[4]; in av1_fdct64_new_sse4_1()
885 btf_32_type0_sse4_1_new(cospi_m32, cospi_p32, x4[5], x4[6], x5[5], x5[6], in av1_fdct64_new_sse4_1()
887 x5[7] = x4[7]; in av1_fdct64_new_sse4_1()
888 x5[8] = _mm_add_epi32(x4[8], x4[11]); in av1_fdct64_new_sse4_1()
889 x5[11] = _mm_sub_epi32(x4[8], x4[11]); in av1_fdct64_new_sse4_1()
[all …]
/external/libmpeg2/common/armv8/
Dideint_spatial_filter_av8.s76 sub x5, x0, #1
80 ld1 {v1.8b}, [x5]
81 add x5, x5, #2
84 ld1 {v2.8b}, [x5]
97 sub x5, x0, #1
101 ld1 {v4.8b}, [x5]
102 add x5, x5, #2
105 ld1 {v5.8b}, [x5]
147 smov x5, v16.s[0]
159 cmp x7, x5
[all …]
Dimpeg2_inter_pred.s110 ldr x5, [x1] //dst->y
114 st1 {v0.8b, v1.8b}, [x5], x3 //Store and increment dst
118 st1 {v0.8b, v1.8b}, [x5], x3 //Store and increment dst
120 st1 {v0.8b, v1.8b}, [x5], x3 //Store and increment dst
122 st1 {v0.8b, v1.8b}, [x5], x3 //Store and increment dst
124 st1 {v0.8b, v1.8b}, [x5], x3 //Store and increment dst
126 st1 {v0.8b, v1.8b}, [x5], x3 //Store and increment dst
128 st1 {v0.8b, v1.8b}, [x5], x3 //Store and increment dst
130 st1 {v0.8b, v1.8b}, [x5], x3 //Store and increment dst
132 st1 {v0.8b, v1.8b}, [x5], x3 //Store and increment dst
[all …]
/external/libhevc/decoder/arm64/
Dihevcd_fmt_conv_420sp_to_420p.s92 mov x8, x5 ////Load u2_width
96 sxtw x5,w5
100 SUB x11,x5,x8 //// Dst Y increment
103 sxtw x5,w5
104 CMP x5,#0 ////skip luma if disable_luma_copy is non-zero
144 sxtw x5,w5
153 SUB x11,x5,x11 //// Dst U and V increment
155 mov x5, x15 ////Load pu1_dest_v
160 csel x4, x5, x4,EQ
161 csel x5, x3, x5,EQ
[all …]
/external/llvm/test/Bitcode/
DbinaryFloatInstructions.3.2.ll8 define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
22 ; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5
23 %res5 = fadd x86_fp80 %x5, %x5
31 …faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){
45 ; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5
46 %res5 = fadd <16 x float> %x5, %x5
51 …ubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){
65 ; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5
66 %res5 = fadd <16 x double> %x5, %x5
71 …void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){
[all …]
DbinaryIntInstructions.3.2.ll8 define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
22 ; CHECK-NEXT: %res5 = add i64 %x5, %x5
23 %res5 = add i64 %x5, %x5
37 define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
51 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5
52 %res5 = add nuw nsw <16 x i8> %x5, %x5
57 …e void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){
71 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5
72 %res5 = add nuw nsw <16 x i16> %x5, %x5
77 …e void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/
DbinaryFloatInstructions.3.2.ll8 define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
22 ; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5
23 %res5 = fadd x86_fp80 %x5, %x5
31 …faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){
45 ; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5
46 %res5 = fadd <16 x float> %x5, %x5
51 …ubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){
65 ; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5
66 %res5 = fadd <16 x double> %x5, %x5
71 …void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){
[all …]
DbinaryIntInstructions.3.2.ll8 define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
22 ; CHECK-NEXT: %res5 = add i64 %x5, %x5
23 %res5 = add i64 %x5, %x5
37 define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
51 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5
52 %res5 = add nuw nsw <16 x i8> %x5, %x5
57 …e void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){
71 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5
72 %res5 = add nuw nsw <16 x i16> %x5, %x5
77 …e void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){
[all …]
/external/libavc/common/armv8/
Dih264_inter_pred_luma_copy_av8.s88 sxtw x5, w5
90 mov x12, x5
106 add x5, x0, x2 //pu1_src_tmp += src_strd
109 ld1 {v0.s}[0], [x5], x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
112 ld1 {v0.s}[0], [x5], x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
115 ld1 {v0.s}[0], [x5], x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
123 sub x0, x5, x11 //pu1_src = pu1_src_tmp
142 add x5, x0, x2 //pu1_src_tmp += src_strd
146 ld1 {v1.8b}, [x5], x2 //vld1_u8(pu1_src_tmp)
149 ld1 {v2.8b}, [x5], x2 //vld1_u8(pu1_src_tmp)
[all …]
Dih264_default_weighted_pred_av8.s118 sxtw x5, w5
136 st1 {v0.s}[0], [x2], x5 //load row 1 in destination
137 st1 {v0.s}[1], [x2], x5 //load row 2 in destination
139 st1 {v1.s}[0], [x2], x5 //load row 3 in destination
140 st1 {v1.s}[1], [x2], x5 //load row 4 in destination
158 st1 {v0.8b}, [x2], x5 //load row 1 in destination
160 st1 {v1.8b}, [x2], x5 //load row 2 in destination
161 st1 {v2.8b}, [x2], x5 //load row 3 in destination
162 st1 {v3.8b}, [x2], x5 //load row 4 in destination
198 st1 {v0.8b, v1.8b}, [x2], x5 //load row 1 in destination
[all …]
/external/libvpx/libvpx/vp9/common/x86/
Dvp9_highbd_iht8x8_add_sse4.c58 __m128i x0[2], x1[2], x2[2], x3[2], x4[2], x5[2], x6[2], x7[2]; in highbd_iadst8_sse4_1() local
71 x5[0] = _mm_sub_epi64(s1[0], s5[0]); in highbd_iadst8_sse4_1()
72 x5[1] = _mm_sub_epi64(s1[1], s5[1]); in highbd_iadst8_sse4_1()
95 x5[0] = dct_const_round_shift_64bit(x5[0]); in highbd_iadst8_sse4_1()
96 x5[1] = dct_const_round_shift_64bit(x5[1]); in highbd_iadst8_sse4_1()
106 x5[0] = pack_4(x5[0], x5[1]); in highbd_iadst8_sse4_1()
116 highbd_iadst_butterfly_sse4_1(x4[0], x5[0], cospi_8_64, cospi_24_64, s4, s5); in highbd_iadst8_sse4_1()
121 x5[0] = _mm_add_epi64(s5[0], s7[0]); in highbd_iadst8_sse4_1()
122 x5[1] = _mm_add_epi64(s5[1], s7[1]); in highbd_iadst8_sse4_1()
129 x5[0] = dct_const_round_shift_64bit(x5[0]); in highbd_iadst8_sse4_1()
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_inv_dit_fft_8pt.s25 MOV x5, #8
33 LD1 {v1.s}[0], [x0], x5
34 LD1 {v2.s}[0], [x6], x5
35 LD1 {v1.s}[1], [x0], x5
36 LD1 {v2.s}[1], [x6], x5
37 LD1 {v3.s}[0], [x0], x5
38 LD1 {v4.s}[0], [x6], x5
39 LD1 {v3.s}[1], [x0], x5
40 LD1 {v4.s}[1], [x6], x5
41 LD1 {v5.s}[0], [x0], x5
[all …]
/external/libavc/common/
Dih264_resi_trans_quant.c125 WORD32 x0, x1, x2, x3, x4, x5, x6, x7; in ih264_resi_trans_quant_4x4() local
135 x5 = pu1_src[1] - pu1_pred[1]; in ih264_resi_trans_quant_4x4()
141 x1 = x5 + x6; in ih264_resi_trans_quant_4x4()
142 x2 = x5 - x6; in ih264_resi_trans_quant_4x4()
162 x5 = pi2_out_tmp[4]; in ih264_resi_trans_quant_4x4()
168 x1 = x5 + x6; in ih264_resi_trans_quant_4x4()
169 x2 = x5 - x6; in ih264_resi_trans_quant_4x4()
273 WORD32 x0, x1, x2, x3, x4, x5, x6, x7; in ih264_resi_trans_quant_chroma_4x4() local
283 x5 = pu1_src[2] - pu1_pred[2]; in ih264_resi_trans_quant_chroma_4x4()
289 x1 = x5 + x6; in ih264_resi_trans_quant_chroma_4x4()
[all …]

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