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Searched refs:xtn (Results 1 – 25 of 92) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-convert-v4f64.ll8 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
10 ; CHECK: xtn v0.4h, v[[MID]].4s
22 ; CHECK-DAG: xtn v[[NA2:[0-9]+]].2s, v[[CONV2]].2d
24 ; CHECK-DAG: xtn v[[NA0:[0-9]+]].2s, v[[CONV0]].2d
26 ; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA2]].4s
28 ; CHECK: xtn v0.8b, v[[TMP1]].8h
48 ; CHECK: xtn
50 ; CHECK: xtn
60 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
62 ; CHECK: xtn v0.4h, v[[MID]].4s
Dcomplex-fp-to-int.ll56 ; CHECK: xtn.4h v0, [[VAL64]]
65 ; CHECK: xtn.4h v0, [[VAL64]]
74 ; CHECK: xtn.4h v0, [[VAL64]]
83 ; CHECK: xtn.4h v0, [[VAL64]]
92 ; CHECK: xtn.2s v0, [[VAL64]]
101 ; CHECK: xtn.2s v0, [[VAL64]]
110 ; CHECK: xtn.2s v0, [[VAL64]]
119 ; CHECK: xtn.2s v0, [[VAL64]]
128 ; CHECK: xtn.2s v0, [[VAL64]]
137 ; CHECK: xtn.2s v0, [[VAL64]]
Dneon-truncStore-extLoad.ll7 ; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
16 ; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
25 ; CHECK: xtn [[TMP:(v[0-9]+)]].4h, v{{[0-9]+}}.4s
26 ; CHECK-NEXT: xtn [[TMP2:(v[0-9]+)]].8b, [[TMP]].8h
35 ; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
Dtrunc-v1i64.ll16 ; CHECK: xtn v0.2s, v0.2d
24 ; CHECK: xtn v0.2s, v0.2d
33 ; CHECK-NOT: xtn
41 ; CHECK-NOT: xtn
50 ; CHECK-NOT: xtn
58 ; CHECK-NOT: xtn
Dfp16-v4-instructions.ll259 ; CHECK-COMMON-NEXT: xtn v0.4h, [[REG2]]
269 ; CHECK-COMMON-NEXT: xtn v0.4h, [[REG2]]
278 ; NOTE: fcvtzs selected here because the xtn shaves the sign bit
280 ; CHECK-COMMON-NEXT: xtn v0.4h, [[REG2]]
290 ; CHECK-COMMON-NEXT: xtn v0.4h, [[REG2]]
302 ; CHECK-CVT: xtn
327 ; CHECK-CVT: xtn
351 ; CHECK-CVT: xtn
375 ; CHECK-CVT: xtn
399 ; CHECK-CVT: xtn
[all …]
Dconcat_vector-truncate-combine.ll11 ; CHECK-NEXT: xtn.4h v0, v0
23 ; CHECK-NEXT: xtn.8b v0, v0
34 ; CHECK-NEXT: xtn.4h v0, v0
Dvcvt-oversize.ll10 ; CHECK-DAG: xtn v[[TMP:[0-9]+]].4h, v[[LSB]].4s
12 ; CHECK-DAG: xtn v0.8b, v[[TMP]].8h
Dsetcc-type-mismatch.ll6 ; CHECK: xtn {{v[0-9]+}}.4h, [[CMP128]].4s
/external/llvm/test/CodeGen/AArch64/
Darm64-convert-v4f64.ll8 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
10 ; CHECK: xtn v0.4h, v[[MID]].4s
22 ; CHECK-DAG: xtn v[[NA2:[0-9]+]].2s, v[[CONV2]].2d
24 ; CHECK-DAG: xtn v[[NA0:[0-9]+]].2s, v[[CONV0]].2d
26 ; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA2]].4s
28 ; CHECK: xtn v0.8b, v[[TMP1]].8h
48 ; CHECK: xtn
50 ; CHECK: xtn
60 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
62 ; CHECK: xtn v0.4h, v[[MID]].4s
Dcomplex-fp-to-int.ll56 ; CHECK: xtn.4h v0, [[VAL64]]
65 ; CHECK: xtn.4h v0, [[VAL64]]
74 ; CHECK: xtn.4h v0, [[VAL64]]
83 ; CHECK: xtn.4h v0, [[VAL64]]
92 ; CHECK: xtn.2s v0, [[VAL64]]
101 ; CHECK: xtn.2s v0, [[VAL64]]
110 ; CHECK: xtn.2s v0, [[VAL64]]
119 ; CHECK: xtn.2s v0, [[VAL64]]
128 ; CHECK: xtn.2s v0, [[VAL64]]
137 ; CHECK: xtn.2s v0, [[VAL64]]
Dtrunc-v1i64.ll16 ; CHECK: xtn v0.2s, v0.2d
24 ; CHECK: xtn v0.2s, v0.2d
33 ; CHECK-NOT: xtn
41 ; CHECK-NOT: xtn
50 ; CHECK-NOT: xtn
58 ; CHECK-NOT: xtn
Dconcat_vector-truncate-combine.ll11 ; CHECK-NEXT: xtn.4h v0, v0
23 ; CHECK-NEXT: xtn.8b v0, v0
34 ; CHECK-NEXT: xtn.4h v0, v0
Dneon-truncStore-extLoad.ll7 ; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
16 ; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
25 ; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
Dvcvt-oversize.ll10 ; CHECK-DAG: xtn v[[TMP:[0-9]+]].4h, v[[LSB]].4s
12 ; CHECK-DAG: xtn v0.8b, v[[TMP]].8h
Dsetcc-type-mismatch.ll6 ; CHECK: xtn {{v[0-9]+}}.4h, [[CMP128]].4s
Dfp16-v8-instructions.ll375 ; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]]
378 ; CHECK-NEXT: xtn v0.8b, [[I16]].8h
389 ; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]]
402 ; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]]
405 ; CHECK-NEXT: xtn v0.8b, [[I16]].8h
416 ; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]]
/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_planar.s214 xtn v27.8b, v27.8h //(1)
231 xtn v30.8b, v30.8h //(2)
248 xtn v28.8b, v28.8h //(3)
264 xtn v25.8b, v25.8h //(4)
281 xtn v16.8b, v16.8h //(5)
298 xtn v18.8b, v18.8h //(6)
350 xtn v26.8b, v26.8h //(7)
353 xtn v24.8b, v24.8h //(8)
390 xtn v27.8b, v27.8h //(1)
408 xtn v30.8b, v30.8h //(2)
[all …]
Dihevc_intra_pred_chroma_planar.s228 xtn v12.8b, v12.8h
230 xtn v13.8b, v28.8h
258 xtn v26.8b, v26.8h
260 xtn v27.8b, v24.8h
282 xtn v22.8b, v22.8h
286 xtn v23.8b, v20.8h
297 xtn v20.8b, v12.8h
298 xtn v21.8b, v28.8h
Dihevc_sao_edge_offset_class1.s197 xtn v20.8b, v20.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
211 xtn v30.8b, v26.8h //II vmovn_s16(pi2_tmp_cur_row.val[0])
245 xtn v30.8b, v26.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
315 xtn v20.8b, v20.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
323 xtn v30.8b, v26.8h //II vmovn_s16(pi2_tmp_cur_row.val[0])
350 xtn v30.8b, v26.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
Dihevc_sao_edge_offset_class0.s234 xtn v18.8b, v18.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
237 xtn v19.8b, v21.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
243 xtn v0.8b, v0.8h //II vmovn_s16(pi2_tmp_cur_row.val[0])
250 xtn v1.8b, v28.8h //II vmovn_s16(pi2_tmp_cur_row.val[1])
324 xtn v28.8b, v28.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
Dihevc_sao_edge_offset_class1_chroma.s243 xtn v20.8b, v20.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
259 xtn v30.8b, v26.8h //II vmovn_s16(pi2_tmp_cur_row.val[0])
305 xtn v30.8b, v26.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
396 xtn v20.8b, v20.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
410 xtn v30.8b, v26.8h //II vmovn_s16(pi2_tmp_cur_row.val[0])
449 xtn v30.8b, v26.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
Dihevc_sao_edge_offset_class0_chroma.s271 xtn v21.8b, v18.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
274 xtn v23.8b, v19.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
306 xtn v28.8b, v28.8h //II vmovn_s16(pi2_tmp_cur_row.val[0])
307 xtn v29.8b, v30.8h //II vmovn_s16(pi2_tmp_cur_row.val[1])
438 xtn v18.8b, v18.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
467 xtn v28.8b, v24.8h //II vmovn_s16(pi2_tmp_cur_row.val[0])
Dihevc_sao_edge_offset_class2.s346 xtn v20.8b, v20.8h //I vmovn_s16(pi2_tmp_cur_row.val[0])
454 xtn v26.8b, v26.8h //II vmovn_s16(pi2_tmp_cur_row.val[0])
460 xtn v20.8b, v20.8h //III vmovn_s16(pi2_tmp_cur_row.val[0])
524 xtn v20.8b, v20.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
664 xtn v28.8b, v28.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
791 xtn v30.8b, v28.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
/external/libavc/common/armv8/
Dih264_resi_trans_quant_av8.s188 xtn v20.4h, v20.4s //narrow row 1
189 xtn v21.4h, v21.4s //narrow row 2
190 xtn v22.4h, v22.4s //narrow row 3
191 xtn v23.4h, v23.4s //narrow row 4
213 xtn v0.8b, v0.8h
214 xtn v1.8b, v1.8h
390 xtn v20.4h, v20.4s //narrow row 1
391 xtn v21.4h, v21.4s //narrow row 2
392 xtn v22.4h, v22.4s //narrow row 3
393 xtn v23.4h, v23.4s //narrow row 4
[all …]
Dih264_ihadamard_scaling_av8.s242 xtn v0.4h, v2.4s //i4_x4 i4_x5 i4_y4 i4_y5
243 xtn v1.4h, v3.4s //i4_x6 i4_x7 i4_y6 i4_y7

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