Home
last modified time | relevance | path

Searched refs:i8 (Results 1 – 25 of 55) sorted by relevance

123

/frameworks/rs/driver/runtime/ll64/
Dallocation.ll6 declare i8* @rsOffset(%struct.rs_allocation* nocapture readonly %a, i32 %sizeOf, i32 %x, i32 %y, i3…
7 declare i8* @rsOffsetNs(%struct.rs_allocation* nocapture readonly %a, i32 %x, i32 %y, i32 %z)
38 define void @rsSetElementAtImpl_char(%struct.rs_allocation* nocapture readonly %a, i8 signext %val,…
39 %1 = tail call i8* @rsOffset(%struct.rs_allocation* %a, i32 1, i32 %x, i32 %y, i32 %z) #2
40 store i8 %val, i8* %1, align 1, !tbaa !21
44 define signext i8 @rsGetElementAtImpl_char(%struct.rs_allocation* nocapture readonly %a, i32 %x, i3…
45 %1 = tail call i8* @rsOffset(%struct.rs_allocation* %a, i32 1, i32 %x, i32 %y, i32 %z) #2
46 %2 = load i8, i8* %1, align 1, !tbaa !21
47 ret i8 %2
52 %1 = tail call i8* @rsOffset(%struct.rs_allocation* %a, i32 2, i32 %x, i32 %y, i32 %z) #2
[all …]
/frameworks/rs/driver/runtime/ll32/
Dallocation.ll1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v…
4 declare i8* @rsOffset([1 x i32] %a.coerce, i32 %sizeOf, i32 %x, i32 %y, i32 %z)
5 declare i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z)
36 define void @rsSetElementAtImpl_char([1 x i32] %a.coerce, i8 signext %val, i32 %x, i32 %y, i32 %z) …
37 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2
38 store i8 %val, i8* %1, align 1, !tbaa !21
42 define signext i8 @rsGetElementAtImpl_char([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 {
43 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2
44 %2 = load i8, i8* %1, align 1, !tbaa !21
45 ret i8 %2
[all …]
/frameworks/rs/rsov/compiler/tests/rs_allocation/
Daccess_same.ll15 @c1 = common global i8 0, align 1
18 define <4 x i8> @k1(<4 x i8> %in) #0 {
20 %0 = extractelement <4 x i8> %in, i32 0
21 %conv = zext i8 %0 to i32
22 %1 = extractelement <4 x i8> %in, i32 1
23 %conv1 = zext i8 %1 to i32
26 …%call = tail call <4 x i8> @_Z21rsGetElementAt_uchar413rs_allocationjj([1 x i32] %2, i32 %conv, i3…
27 %3 = extractelement <4 x i8> %in, i32 2
28 %conv2 = zext i8 %3 to i32
29 %4 = extractelement <4 x i8> %in, i32 3
[all …]
Dmulti_read.ll16 @c1 = common global i8 0, align 1
19 define <4 x i8> @k1(<4 x i8> %in) #0 {
21 %0 = extractelement <4 x i8> %in, i32 0
22 %conv = zext i8 %0 to i32
23 %1 = extractelement <4 x i8> %in, i32 1
24 %conv1 = zext i8 %1 to i32
27 …%call = tail call <4 x i8> @_Z21rsGetElementAt_uchar413rs_allocationjj([1 x i32] %2, i32 %conv, i3…
28 %3 = extractelement <4 x i8> %in, i32 2
29 %conv2 = zext i8 %3 to i32
30 %4 = extractelement <4 x i8> %in, i32 3
[all …]
Dread.ll15 @c1 = common global i8 0, align 1
18 define <4 x i8> @k1(<4 x i8> %in) #0 {
20 %0 = extractelement <4 x i8> %in, i32 0
21 %conv = zext i8 %0 to i32
22 %1 = extractelement <4 x i8> %in, i32 1
23 %conv1 = zext i8 %1 to i32
26 …%call = tail call <4 x i8> @_Z21rsGetElementAt_uchar413rs_allocationjj([1 x i32] %2, i32 %conv, i3…
27 %3 = load i8, i8* @c1, align 1, !tbaa !13
28 %conv2 = zext i8 %3 to i32
29 %4 = extractelement <4 x i8> %call, i32 2
[all …]
Dread_write.ll16 @c1 = common global i8 0, align 1
19 define <4 x i8> @k1(<4 x i8> %in, i32 %x, i32 %y) #0 {
23 …%call = tail call <4 x i8> @_Z21rsGetElementAt_uchar413rs_allocationjj([1 x i32] %0, i32 %x, i32 %…
24 %1 = load i8, i8* @c1, align 1, !tbaa !15
25 %splat.splatinsert = insertelement <4 x i8> undef, i8 %1, i32 0
26 …%splat.splat = shufflevector <4 x i8> %splat.splatinsert, <4 x i8> undef, <4 x i32> zeroinitializer
27 %add = add <4 x i8> %call, %in
28 %add1 = add <4 x i8> %add, %splat.splat
31 …tail call void @_Z21rsSetElementAt_uchar413rs_allocationDv4_hjj([1 x i32] %2, <4 x i8> %add1, i32 …
32 ret <4 x i8> %in
[all …]
Dwrite.ll15 @c1 = common global i8 0, align 1
18 define <4 x i8> @k1(<4 x i8> %in, i32 %x, i32 %y) #0 {
20 %0 = load i8, i8* @c1, align 1, !tbaa !13
21 %splat.splatinsert = insertelement <4 x i8> undef, i8 %0, i32 0
22 …%splat.splat = shufflevector <4 x i8> %splat.splatinsert, <4 x i8> undef, <4 x i32> zeroinitializer
23 %add = add <4 x i8> %splat.splat, %in
26 …tail call void @_Z21rsSetElementAt_uchar413rs_allocationDv4_hjj([1 x i32] %1, <4 x i8> %add, i32 %…
27 ret <4 x i8> %in
30 declare void @_Z21rsSetElementAt_uchar413rs_allocationDv4_hjj([1 x i32], <4 x i8>, i32, i32) #1
Dcopy_coords.ll11 define <4 x i8> @copy_coords(<4 x i8> %in, i32 %x, i32 %y) #0 {
13 %conv = trunc i32 %x to i8
14 %0 = insertelement <4 x i8> %in, i8 %conv, i32 0
15 %conv1 = trunc i32 %y to i8
16 %1 = insertelement <4 x i8> %0, i8 %conv1, i32 1
17 ret <4 x i8> %1
Dgetdimx_64.ll7 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
34 %0 = bitcast %struct.rs_allocation.1* %tmp to i8*
35 …call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.rs_allocation.1* @g to i8*), i64…
43 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, …
/frameworks/rs/rsov/compiler/tests/multi_function/
Dblend_mf.ll23 define <4 x i8> @setImageAlpha(<4 x i8> %in) #1 {
25 %call = tail call <4 x i32> @_Z13convert_uint4Dv4_h(<4 x i8> %in) #2
28 %call1 = tail call <4 x i8> @_Z14convert_uchar4Dv4_j(<4 x i32> %shr) #2
29 %call2 = tail call fastcc <4 x i8> @twice(<4 x i8> %call1)
30 %0 = insertelement <4 x i8> %call2, i8 37, i32 3
31 ret <4 x i8> %0
35 define internal fastcc <4 x i8> @twice(<4 x i8> %in) #0 {
37 %mul = shl <4 x i8> %in, <i8 1, i8 1, i8 1, i8 1>
38 ret <4 x i8> %mul
42 declare <4 x i8> @_Z14convert_uchar4Dv4_j(<4 x i32>) #1
[all …]
/frameworks/compile/libbcc/tests/libbcc/
Dtest_reduce_general_metadata.ll46 …i8*] [i8* bitcast (void (<2 x i32>*)* @fz2Init to i8*), i8* bitcast (void ([256 x i32]*, [256 x i3…
90 %1 = bitcast %struct.MinAndMax.0* %accum to i8*
91 …tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast (%struct.MinAndMax.0* @fMMInit.r to …
96 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #0
241 define internal void @hsgAccum([256 x i32]* nocapture %h, i8 %in) #0 {
242 %1 = zext i8 %in to i64
Dtest_reduce_general_cleanup.ll29 @.rs.reduce_fn.aiAccum = global i8* bitcast (void (i32*, i32)* @aiAccum to i8*), align 4
30 @.rs.reduce_fn.dpAccum = global i8* bitcast (void (float*, float, float)* @dpAccum to i8*), align 4
31 @.rs.reduce_fn.dpSum = global i8* bitcast (void (float*, float*)* @dpSum to i8*), align 4
32 @.rs.reduce_fn.fMMInit = global i8* bitcast (void (%struct.MinAndMax*)* @fMMInit to i8*), align 4
33 @.rs.reduce_fn.fMMAccumulator = global i8* bitcast (void (%struct.MinAndMax*, float, i32)* @fMMAccu…
34 @.rs.reduce_fn.fMMCombiner = global i8* bitcast (void (%struct.MinAndMax*, %struct.MinAndMax*)* @fM…
35 ….rs.reduce_fn.fMMOutConverter = global i8* bitcast (void (<2 x i32>*, %struct.MinAndMax*)* @fMMOut…
36 @.rs.reduce_fn.fzInit = global i8* bitcast (void (i32*)* @fzInit to i8*), align 4
37 @.rs.reduce_fn.fzAccum = global i8* bitcast (void (i32*, i32, i32)* @fzAccum to i8*), align 4
38 @.rs.reduce_fn.fzCombine = global i8* bitcast (void (i32*, i32*)* @fzCombine to i8*), align 4
[all …]
Dtest_slang_version_info.ll54 define <4 x i8> @swizzle(<4 x i8> %in) #0 !dbg !4 {
55 %1 = alloca <4 x i8>, align 4
56 %result = alloca <4 x i8>, align 4
57 store <4 x i8> %in, <4 x i8>* %1, align 4
58 call void @llvm.dbg.declare(metadata <4 x i8>* %1, metadata !27, metadata !28), !dbg !29
59 call void @llvm.dbg.declare(metadata <4 x i8>* %result, metadata !30, metadata !28), !dbg !31
60 %2 = load <4 x i8>, <4 x i8>* %1, align 4, !dbg !31
61 %3 = shufflevector <4 x i8> %2, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>, !dbg !31
62 store <4 x i8> %3, <4 x i8>* %result, align 4, !dbg !31
63 %4 = load <4 x i8>, <4 x i8>* %result, align 4, !dbg !32
[all …]
Dgetelementptr.ll31 ; CHECK: load i8*, i8** %input_buf.gep
33 ; CHECK: load i8*, i8** %out_buf.gep
47 ; CHECK: load i8*, i8** %out_buf.gep
53 ; CHECK: load i8*, i8** %input_buf.gep
55 ; CHECK: load i8*, i8** %input_buf.gep1
Dtbaa-through-alloca.ll39 %5 = bitcast %struct.int5.0* %agg.result to i8*
40 %6 = bitcast %struct.int5.0* %in to i8*
41 …tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %5, i8* %6, i64 20, i32 4, i1 false), !tbaa.struct !…
46 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #0
/frameworks/rs/rsov/compiler/tests/image/
Dblend.ll14 @alpha = global i8 0, align 1
17 define <4 x i8> @setImageAlpha(<4 x i8> %in, i32 %x, i32 %y) #0 {
19 %call = tail call <4 x i32> @_Z13convert_uint4Dv4_h(<4 x i8> %in) #2
20 %0 = load i8, i8* @alpha, align 1, !tbaa !11
21 %conv = zext i8 %0 to i32
26 %call1 = tail call <4 x i8> @_Z14convert_uchar4Dv4_j(<4 x i32> %shr) #2
27 %1 = insertelement <4 x i8> %call1, i8 %0, i32 3
28 ret <4 x i8> %1
32 declare <4 x i8> @_Z14convert_uchar4Dv4_j(<4 x i32>) #1
35 declare <4 x i32> @_Z13convert_uint4Dv4_h(<4 x i8>) #1
Dcontrast.ll37 define <4 x i8> @contrast(<4 x i8> %in) #2 {
39 %0 = shufflevector <4 x i8> %in, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
40 %call = tail call <3 x float> @_Z14convert_float3Dv3_h(<3 x i8> %0) #4
50 %call5 = tail call <3 x i8> @_Z14convert_uchar3Dv3_f(<3 x float> %call4) #4
51 %3 = shufflevector <3 x i8> %call5, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
52 %4 = insertelement <4 x i8> %3, i8 -1, i32 3
53 ret <4 x i8> %4
57 declare <3 x float> @_Z14convert_float3Dv3_h(<3 x i8>) #1
60 declare <3 x i8> @_Z14convert_uchar3Dv3_f(<3 x float>) #1
Dcopy.ll10 define <4 x i8> @copy(<4 x i8> %v_in) #0 {
12 ret <4 x i8> %v_in
/frameworks/rs/driver/runtime/arch/
Dneon.ll1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v…
26 declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
30 declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
34 declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
370 define signext i8 @_Z3maxcc(i8 signext %v1, i8 signext %v2) nounwind readnone {
371 %1 = icmp sgt i8 %v1, %v2
372 %2 = select i1 %1, i8 %v1, i8 %v2
373 ret i8 %2
376 define <2 x i8> @_Z3maxDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
377 %1 = sext <2 x i8> %v1 to <2 x i32>
[all …]
Dasimd.ll26 declare <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
30 declare <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
366 define signext i8 @_Z3maxcc(i8 signext %v1, i8 signext %v2) nounwind readnone {
367 %1 = icmp sgt i8 %v1, %v2
368 %2 = select i1 %1, i8 %v1, i8 %v2
369 ret i8 %2
372 define <2 x i8> @_Z3maxDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
373 %1 = sext <2 x i8> %v1 to <2 x i32>
374 %2 = sext <2 x i8> %v2 to <2 x i32>
376 %4 = trunc <2 x i32> %3 to <2 x i8>
[all …]
/frameworks/rs/cpu_ref/
DrsCpuIntrinsics_neon_YuvToRGB.S34 vmov.i8 d15, #149
39 vmov.i8 d14, #50
40 vmov.i8 d15, #104
52 vmov.i8 d14, #204
53 vmov.i8 d15, #254
96 vmov.i8 q3, #0xff
137 vmov.i8 q8, #0
138 vmov.i8 q10, #0
/frameworks/rs/script_api/
Drs_convert.spec28 t: u8, u16, u32, i8, i16, i32, f32
29 t: u8, u16, u32, i8, i16, i32, f32
61 t: u8, u16, u32, i8, i16, i32, f32
70 t: u8, u16, u32, i8, i16, i32, f32
81 t: u8, u16, u32, u64, i8, i16, i32, i64, f16, f32, f64
90 t: u8, u16, u32, u64, i8, i16, i32, i64, f32, f64
/frameworks/rs/rsov/compiler/tests/single_kernel/
Dmixed.ll8 @.str = private unnamed_addr constant [24 x i8] c"test_root_output FAILED\00", align 1
15 …tail call void @_Z7rsDebugPKci(i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str, i32 0, i32…
19 declare void @_Z7rsDebugPKci(i8*, i32) local_unnamed_addr #1
/frameworks/ml/nn/tools/test_generator/tests/P_vts_internal/
Dadd_internal.mod.py25 i8 = Input("i8", ("TENSOR_FLOAT32", [2])) # input 0 variable
51 model.Operation("ADD", i7, i8, act).To(o1)
62 i8: [0, 0]
/frameworks/ml/nn/tools/test_generator/tests/P_internal/
Dadd_internal.mod.py25 i8 = Input("i8", ("TENSOR_FLOAT32", [2])) # input 0 variable
51 model.Operation("ADD", i7, i8, act).To(o1)
62 i8: [0, 0]

123