1 /* 2 * Broadcom device-specific manifest constants. 3 * 4 * Copyright (C) 1999-2013, Broadcom Corporation 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: bcmdevs.h 387183 2013-02-24 07:42:07Z $ 19 */ 20 21 #ifndef _BCMDEVS_H 22 #define _BCMDEVS_H 23 24 /* PCI vendor IDs */ 25 #define VENDOR_EPIGRAM 0xfeda 26 #define VENDOR_BROADCOM 0x14e4 27 #define VENDOR_3COM 0x10b7 28 #define VENDOR_NETGEAR 0x1385 29 #define VENDOR_DIAMOND 0x1092 30 #define VENDOR_INTEL 0x8086 31 #define VENDOR_DELL 0x1028 32 #define VENDOR_HP 0x103c 33 #define VENDOR_HP_COMPAQ 0x0e11 34 #define VENDOR_APPLE 0x106b 35 #define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */ 36 #define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */ 37 #define VENDOR_TI 0x104c /* Texas Instruments */ 38 #define VENDOR_RICOH 0x1180 /* Ricoh */ 39 #define VENDOR_JMICRON 0x197b 40 41 42 /* PCMCIA vendor IDs */ 43 #define VENDOR_BROADCOM_PCMCIA 0x02d0 44 45 /* SDIO vendor IDs */ 46 #define VENDOR_BROADCOM_SDIO 0x00BF 47 48 /* DONGLE VID/PIDs */ 49 #define BCM_DNGL_VID 0x0a5c 50 #define BCM_DNGL_BL_PID_4328 0xbd12 51 #define BCM_DNGL_BL_PID_4322 0xbd13 52 #define BCM_DNGL_BL_PID_4319 0xbd16 53 #define BCM_DNGL_BL_PID_43236 0xbd17 54 #define BCM_DNGL_BL_PID_4332 0xbd18 55 #define BCM_DNGL_BL_PID_4330 0xbd19 56 #define BCM_DNGL_BL_PID_4334 0xbd1a 57 #define BCM_DNGL_BL_PID_43239 0xbd1b 58 #define BCM_DNGL_BL_PID_4324 0xbd1c 59 #define BCM_DNGL_BL_PID_4360 0xbd1d 60 #define BCM_DNGL_BL_PID_43143 0xbd1e 61 #define BCM_DNGL_BL_PID_43242 0xbd1f 62 #define BCM_DNGL_BL_PID_43342 0xbd21 63 #define BCM_DNGL_BL_PID_4335 0xbd20 64 #define BCM_DNGL_BL_PID_4350 0xbd23 65 #define BCM_DNGL_BL_PID_43341 0xbd22 66 67 #define BCM_DNGL_BDC_PID 0x0bdc 68 #define BCM_DNGL_JTAG_PID 0x4a44 69 70 /* HW USB BLOCK [CPULESS USB] PIDs */ 71 #define BCM_HWUSB_PID_43239 43239 72 73 /* PCI Device IDs */ 74 #define BCM4210_DEVICE_ID 0x1072 /* never used */ 75 #define BCM4230_DEVICE_ID 0x1086 /* never used */ 76 #define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */ 77 #define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */ 78 #define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */ 79 #define BCM4211_DEVICE_ID 0x4211 80 #define BCM4231_DEVICE_ID 0x4231 81 #define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */ 82 #define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */ 83 #define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */ 84 #define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */ 85 #define BCM4328_D11DUAL_ID 0x4314 /* 4328/4312 802.11a/g id */ 86 #define BCM4328_D11G_ID 0x4315 /* 4328/4312 802.11g id */ 87 #define BCM4328_D11A_ID 0x4316 /* 4328/4312 802.11a id */ 88 #define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */ 89 #define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */ 90 #define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */ 91 #define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */ 92 #define BCM4325_D11G_ID 0x431c /* 4325 802.11g id */ 93 #define BCM4325_D11A_ID 0x431d /* 4325 802.11a id */ 94 #define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */ 95 #define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */ 96 #define BCM4306_UART_ID 0x4322 /* 4306 uart */ 97 #define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */ 98 #define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */ 99 #define BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G_ID; INF w/loose binding war */ 100 #define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */ 101 #define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */ 102 #define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */ 103 #define BCM4322_D11N_ID 0x432b /* 4322 802.11n dualband device */ 104 #define BCM4322_D11N2G_ID 0x432c /* 4322 802.11n 2.4GHz device */ 105 #define BCM4322_D11N5G_ID 0x432d /* 4322 802.11n 5GHz device */ 106 #define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */ 107 #define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */ 108 #define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */ 109 #define BCM4315_D11DUAL_ID 0x4334 /* 4315 802.11a/g id */ 110 #define BCM4315_D11G_ID 0x4335 /* 4315 802.11g id */ 111 #define BCM4315_D11A_ID 0x4336 /* 4315 802.11a id */ 112 #define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */ 113 #define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */ 114 #define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */ 115 #define BCM43231_D11N2G_ID 0x4340 /* 43231 802.11n 2.4GHz device */ 116 #define BCM43221_D11N2G_ID 0x4341 /* 43221 802.11n 2.4GHz device */ 117 #define BCM43222_D11N_ID 0x4350 /* 43222 802.11n dualband device */ 118 #define BCM43222_D11N2G_ID 0x4351 /* 43222 802.11n 2.4GHz device */ 119 #define BCM43222_D11N5G_ID 0x4352 /* 43222 802.11n 5GHz device */ 120 #define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */ 121 #define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */ 122 #define BCM43226_D11N_ID 0x4354 /* 43226 802.11n dualband device */ 123 #define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */ 124 #define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */ 125 #define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */ 126 #define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */ 127 #define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */ 128 #define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */ 129 #define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */ 130 #define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */ 131 #define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */ 132 #define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */ 133 #define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */ 134 #define BCM6362_D11N2G_ID 0x433f /* 6362 802.11n 2.4Ghz band id */ 135 #define BCM6362_D11N5G_ID 0x434f /* 6362 802.11n 5Ghz band id */ 136 #define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */ 137 #define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */ 138 #define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */ 139 #define BCM43237_D11N_ID 0x4355 /* 43237 802.11n dualband device */ 140 #define BCM43237_D11N5G_ID 0x4356 /* 43237 802.11n 5GHz device */ 141 #define BCM43227_D11N2G_ID 0x4358 /* 43228 802.11n 2.4GHz device */ 142 #define BCM43228_D11N_ID 0x4359 /* 43228 802.11n DualBand device */ 143 #define BCM43228_D11N5G_ID 0x435a /* 43228 802.11n 5GHz device */ 144 #define BCM43362_D11N_ID 0x4363 /* 43362 802.11n 2.4GHz device */ 145 #define BCM43239_D11N_ID 0x4370 /* 43239 802.11n dualband device */ 146 #define BCM4324_D11N_ID 0x4374 /* 4324 802.11n dualband device */ 147 #define BCM43217_D11N2G_ID 0x43a9 /* 43217 802.11n 2.4GHz device */ 148 #define BCM43131_D11N2G_ID 0x43aa /* 43131 802.11n 2.4GHz device */ 149 #define BCM4314_D11N2G_ID 0x4364 /* 4314 802.11n 2.4G device */ 150 #define BCM43142_D11N2G_ID 0x4365 /* 43142 802.11n 2.4G device */ 151 #define BCM43143_D11N2G_ID 0x4366 /* 43143 802.11n 2.4G device */ 152 #define BCM4334_D11N_ID 0x4380 /* 4334 802.11n dualband device */ 153 #define BCM4334_D11N2G_ID 0x4381 /* 4334 802.11n 2.4G device */ 154 #define BCM4334_D11N5G_ID 0x4382 /* 4334 802.11n 5G device */ 155 #define BCM43342_D11N_ID 0x4383 /* 43342 802.11n dualband device */ 156 #define BCM43342_D11N2G_ID 0x4384 /* 43342 802.11n 2.4G device */ 157 #define BCM43342_D11N5G_ID 0x4385 /* 43342 802.11n 5G device */ 158 #define BCM43341_D11N_ID 0x4386 /* 43341 802.11n dualband device */ 159 #define BCM43341_D11N2G_ID 0x4387 /* 43341 802.11n 2.4G device */ 160 #define BCM43341_D11N5G_ID 0x4388 /* 43341 802.11n 5G device */ 161 #define BCM4360_D11AC_ID 0x43a0 162 #define BCM4360_D11AC2G_ID 0x43a1 163 #define BCM4360_D11AC5G_ID 0x43a2 164 #define BCM4335_D11AC_ID 0x43ae 165 #define BCM4335_D11AC2G_ID 0x43af 166 #define BCM4335_D11AC5G_ID 0x43b0 167 #define BCM4352_D11AC_ID 0x43b1 /* 4352 802.11ac dualband device */ 168 #define BCM4352_D11AC2G_ID 0x43b2 /* 4352 802.11ac 2.4G device */ 169 #define BCM4352_D11AC5G_ID 0x43b3 /* 4352 802.11ac 5G device */ 170 171 /* PCI Subsystem ID */ 172 #define BCM943228HMB_SSID_VEN1 0x0607 173 #define BCM94313HMGBL_SSID_VEN1 0x0608 174 #define BCM94313HMG_SSID_VEN1 0x0609 175 #define BCM943142HM_SSID_VEN1 0x0611 176 177 #define BCM43143_D11N2G_ID 0x4366 /* 43143 802.11n 2.4G device */ 178 179 #define BCM43242_D11N_ID 0x4367 /* 43242 802.11n dualband device */ 180 #define BCM43242_D11N2G_ID 0x4368 /* 43242 802.11n 2.4G device */ 181 #define BCM43242_D11N5G_ID 0x4369 /* 43242 802.11n 5G device */ 182 183 #define BCM4350_D11AC_ID 0x43a3 184 #define BCM4350_D11AC2G_ID 0x43a4 185 #define BCM4350_D11AC5G_ID 0x43a5 186 187 188 #define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */ 189 #define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */ 190 #define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */ 191 #define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */ 192 #define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */ 193 #define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */ 194 #define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */ 195 #define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */ 196 #define BCM_SPIH_ID 0x43f6 /* Synopsis SPI Host Controller */ 197 #define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */ 198 #define BCM_JTAGM2_ID 0x43f9 /* BCM alternate jtagm device id */ 199 #define SDHCI_FPGA_ID 0x43fa /* Standard SDIO Host Controller FPGA */ 200 #define BCM4402_ENET_ID 0x4402 /* 4402 enet */ 201 #define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */ 202 #define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */ 203 #define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */ 204 #define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */ 205 #define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */ 206 #define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ 207 #define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */ 208 #define BCM47XX_AUDIO_ID 0x4711 /* 47xx audio codec */ 209 #define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */ 210 #define BCM47XX_ENET_ID 0x4713 /* 47xx enet */ 211 #define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */ 212 #define BCM47XX_GMAC_ID 0x4715 /* 47xx Unimac based GbE */ 213 #define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */ 214 #define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */ 215 #define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */ 216 #define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */ 217 #define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */ 218 #define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */ 219 #define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */ 220 #define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */ 221 #define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */ 222 #define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */ 223 #define BCM4716_DEVICE_ID 0x4722 /* 4716 base devid */ 224 #define BCM47XX_USB30H_ID 0x472a /* 47xx usb 3.0 host */ 225 #define BCM47XX_USB30D_ID 0x472b /* 47xx usb 3.0 device */ 226 #define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */ 227 #define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */ 228 #define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */ 229 #define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */ 230 #define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */ 231 #define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */ 232 #define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */ 233 #define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */ 234 #define R5C822_SDIOH_ID 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */ 235 #define JMICRON_SDIOH_ID 0x2381 /* JMicron Standard SDIO Host Controller */ 236 237 /* Chip IDs */ 238 #define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */ 239 #define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */ 240 #define BCM43111_CHIP_ID 43111 /* 43111 chipcommon chipid (OTP chipid) */ 241 #define BCM43112_CHIP_ID 43112 /* 43112 chipcommon chipid (OTP chipid) */ 242 #define BCM4312_CHIP_ID 0x4312 /* 4312 chipcommon chipid */ 243 #define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */ 244 #define BCM43131_CHIP_ID 43131 /* 43131 chip id (OTP chipid) */ 245 #define BCM4315_CHIP_ID 0x4315 /* 4315 chip id */ 246 #define BCM4318_CHIP_ID 0x4318 /* 4318 chipcommon chipid */ 247 #define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */ 248 #define BCM4320_CHIP_ID 0x4320 /* 4320 chipcommon chipid */ 249 #define BCM4321_CHIP_ID 0x4321 /* 4321 chipcommon chipid */ 250 #define BCM43217_CHIP_ID 43217 /* 43217 chip id (OTP chipid) */ 251 #define BCM4322_CHIP_ID 0x4322 /* 4322 chipcommon chipid */ 252 #define BCM43221_CHIP_ID 43221 /* 43221 chipcommon chipid (OTP chipid) */ 253 #define BCM43222_CHIP_ID 43222 /* 43222 chipcommon chipid */ 254 #define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */ 255 #define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */ 256 #define BCM43227_CHIP_ID 43227 /* 43227 chipcommon chipid */ 257 #define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */ 258 #define BCM43226_CHIP_ID 43226 /* 43226 chipcommon chipid */ 259 #define BCM43231_CHIP_ID 43231 /* 43231 chipcommon chipid (OTP chipid) */ 260 #define BCM43234_CHIP_ID 43234 /* 43234 chipcommon chipid */ 261 #define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */ 262 #define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */ 263 #define BCM43237_CHIP_ID 43237 /* 43237 chipcommon chipid */ 264 #define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */ 265 #define BCM43239_CHIP_ID 43239 /* 43239 chipcommon chipid */ 266 #define BCM43420_CHIP_ID 43420 /* 43222 chipcommon chipid (OTP, RBBU) */ 267 #define BCM43421_CHIP_ID 43421 /* 43224 chipcommon chipid (OTP, RBBU) */ 268 #define BCM43428_CHIP_ID 43428 /* 43228 chipcommon chipid (OTP, RBBU) */ 269 #define BCM43431_CHIP_ID 43431 /* 4331 chipcommon chipid (OTP, RBBU) */ 270 #define BCM43460_CHIP_ID 43460 /* 4360 chipcommon chipid (OTP, RBBU) */ 271 #define BCM4325_CHIP_ID 0x4325 /* 4325 chip id */ 272 #define BCM4328_CHIP_ID 0x4328 /* 4328 chip id */ 273 #define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */ 274 #define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */ 275 #define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */ 276 #define BCM43362_CHIP_ID 43362 /* 43362 chipcommon chipid */ 277 #define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */ 278 #define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */ 279 #define BCM4314_CHIP_ID 0x4314 /* 4314 chipcommon chipid */ 280 #define BCM43142_CHIP_ID 43142 /* 43142 chipcommon chipid */ 281 #define BCM43143_CHIP_ID 43143 /* 43143 chipcommon chipid */ 282 #define BCM4324_CHIP_ID 0x4324 /* 4324 chipcommon chipid */ 283 #define BCM43242_CHIP_ID 43242 /* 43242 chipcommon chipid */ 284 #define BCM43243_CHIP_ID 43243 /* 43243 chipcommon chipid */ 285 #define BCM4334_CHIP_ID 0x4334 /* 4334 chipcommon chipid */ 286 #define BCM4335_CHIP_ID 0x4335 /* 4335 chipcommon chipid */ 287 #define BCM4360_CHIP_ID 0x4360 /* 4360 chipcommon chipid */ 288 #define BCM4352_CHIP_ID 0x4352 /* 4352 chipcommon chipid */ 289 #define BCM43526_CHIP_ID 0xAA06 290 #define BCM43341_CHIP_ID 43341 /* 43341 chipcommon chipid */ 291 #define BCM43342_CHIP_ID 43342 /* 43342 chipcommon chipid */ 292 #define BCM4335_CHIP_ID 0x4335 293 #define BCM4350_CHIP_ID 0x4350 /* 4350 chipcommon chipid */ 294 295 #define BCM4342_CHIP_ID 4342 /* 4342 chipcommon chipid (OTP, RBBU) */ 296 #define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */ 297 #define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */ 298 #define BCM4706_CHIP_ID 0x5300 /* 4706 chipcommon chipid */ 299 #define BCM4707_CHIP_ID 53010 /* 4707 chipcommon chipid */ 300 #define BCM53018_CHIP_ID 53018 /* 53018 chipcommon chipid */ 301 #define BCM4707_CHIP(chipid) (((chipid) == BCM4707_CHIP_ID) || ((chipid) == BCM53018_CHIP_ID)) 302 #define BCM4710_CHIP_ID 0x4710 /* 4710 chipid */ 303 #define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */ 304 #define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */ 305 #define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */ 306 #define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */ 307 #define BCM4749_CHIP_ID 0x4749 /* 5357 chipcommon chipid (OTP, RBBU) */ 308 #define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */ 309 #define BCM5350_CHIP_ID 0x5350 /* 5350 chipcommon chipid */ 310 #define BCM5352_CHIP_ID 0x5352 /* 5352 chipcommon chipid */ 311 #define BCM5354_CHIP_ID 0x5354 /* 5354 chipcommon chipid */ 312 #define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */ 313 #define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */ 314 #define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */ 315 #define BCM53572_CHIP_ID 53572 /* 53572 chipcommon chipid */ 316 317 /* Package IDs */ 318 #define BCM4303_PKG_ID 2 /* 4303 package id */ 319 #define BCM4309_PKG_ID 1 /* 4309 package id */ 320 #define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */ 321 #define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */ 322 #define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */ 323 #define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */ 324 #define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */ 325 #define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */ 326 #define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */ 327 #define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */ 328 #define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */ 329 #define BCM5354E_PKG_ID 1 /* 5354E package id */ 330 #define BCM4716_PKG_ID 8 /* 4716 package id */ 331 #define BCM4717_PKG_ID 9 /* 4717 package id */ 332 #define BCM4718_PKG_ID 10 /* 4718 package id */ 333 #define BCM5356_PKG_NONMODE 1 /* 5356 package without nmode suppport */ 334 #define BCM5358U_PKG_ID 8 /* 5358U package id */ 335 #define BCM5358_PKG_ID 9 /* 5358 package id */ 336 #define BCM47186_PKG_ID 10 /* 47186 package id */ 337 #define BCM5357_PKG_ID 11 /* 5357 package id */ 338 #define BCM5356U_PKG_ID 12 /* 5356U package id */ 339 #define BCM53572_PKG_ID 8 /* 53572 package id */ 340 #define BCM5357C0_PKG_ID 8 /* 5357c0 package id (the same as 53572) */ 341 #define BCM47188_PKG_ID 9 /* 47188 package id */ 342 #define BCM5358C0_PKG_ID 0xa /* 5358c0 package id */ 343 #define BCM5356C0_PKG_ID 0xb /* 5356c0 package id */ 344 #define BCM4331TT_PKG_ID 8 /* 4331 12x12 package id */ 345 #define BCM4331TN_PKG_ID 9 /* 4331 12x9 package id */ 346 #define BCM4331TNA0_PKG_ID 0xb /* 4331 12x9 package id */ 347 #define BCM4706L_PKG_ID 1 /* 4706L package id */ 348 349 #define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */ 350 #define HDLSIM_PKG_ID 14 /* HDL simulator package id */ 351 #define HWSIM_PKG_ID 15 /* Hardware simulator package id */ 352 #define BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */ 353 #define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */ 354 #define BCM4336_WLBGA_PKG_ID 0x8 355 #define BCM4330_WLBGA_PKG_ID 0x0 356 #define BCM4314PCIE_ARM_PKG_ID (8 | 0) /* 4314 QFN PCI package id, bit 3 tie high */ 357 #define BCM4314SDIO_PKG_ID (8 | 1) /* 4314 QFN SDIO package id */ 358 #define BCM4314PCIE_PKG_ID (8 | 2) /* 4314 QFN PCI (ARM-less) package id */ 359 #define BCM4314SDIO_ARM_PKG_ID (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */ 360 #define BCM4314SDIO_FPBGA_PKG_ID (8 | 4) /* 4314 FpBGA SDIO package id */ 361 #define BCM4314DEV_PKG_ID (8 | 6) /* 4314 Developement package id */ 362 363 #define BCM4707_PKG_ID 1 /* 4707 package id */ 364 #define BCM4708_PKG_ID 2 /* 4708 package id */ 365 #define BCM4709_PKG_ID 0 /* 4709 package id */ 366 367 #define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */ 368 #define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */ 369 370 #define BCM4335_WLCSP_PKG_ID (0x0) /* WLCSP Module/Mobile SDIO/HSIC. */ 371 #define BCM4335_FCBGA_PKG_ID (0x1) /* FCBGA PC/Embeded/Media PCIE/SDIO */ 372 #define BCM4335_WLBGA_PKG_ID (0x2) /* WLBGA COB/Mobile SDIO/HSIC. */ 373 #define BCM4335_FCBGAD_PKG_ID (0x3) /* FCBGA Debug Debug/Dev All if's. */ 374 #define BCM4335_PKG_MASK (0x3) 375 376 /* boardflags */ 377 #define BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */ 378 #define BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */ 379 #define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */ 380 #define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication, UNUSED */ 381 #define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */ 382 #define BFL_DIS_256QAM 0x00000008 383 #define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */ 384 #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ 385 #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ 386 #define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */ 387 #define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */ 388 #define BFL_LTECOEX 0x00000200 /* Board has LTE coex capability */ 389 #define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ 390 #define BFL_FEM 0x00000800 /* Board supports the Front End Module */ 391 #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ 392 #define BFL_HGPA 0x00002000 /* Board has a high gain PA */ 393 #define BFL_BTC2WIRE_ALTGPIO 0x00004000 394 /* Board's BTC 2wire is in the alternate gpios OBSLETE */ 395 #define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ 396 #define BFL_NOPA 0x00010000 /* Board has no PA */ 397 #define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */ 398 #define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */ 399 #define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */ 400 #define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */ 401 #define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */ 402 #define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */ 403 #define BFL_RXCHAIN_OFF_BT 0x00400000 /* one rxchain is to be shut off when BT is active */ 404 #define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */ 405 #define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */ 406 #define BFL_PALDO 0x02000000 /* Power topology uses PALDO */ 407 #define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */ 408 #define BFL_FASTPWR 0x08000000 409 #define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */ 410 #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ 411 #define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */ 412 #define BFL_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ 413 #define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */ 414 #define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field 415 * when this flag is set 416 */ 417 #define BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */ 418 419 /* boardflags2 */ 420 #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */ 421 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ 422 #define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */ 423 #define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */ 424 #define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */ 425 #define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */ 426 #define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */ 427 #define BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */ 428 #define BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace 429 * BFL2_BTC3WIRE 430 */ 431 #define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */ 432 #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */ 433 #define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */ 434 #define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */ 435 #define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ 436 #define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */ 437 #define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */ 438 #define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */ 439 #define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */ 440 #define BFL2_IPALVLSHIFT_3P3 0x00020000 441 #define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */ 442 #define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio on */ 443 /* Most drivers will turn it off without this flag */ 444 /* to save power. */ 445 446 #define BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */ 447 #define BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */ 448 #define BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */ 449 #define BFL2_BT_SHARE_ANT0 0x00800000 /* WLAN/BT share antenna 0 */ 450 #define BFL2_BT_SHARE_BM_BIT0 0x00800000 /* bit 0 of WLAN/BT shared core bitmap */ 451 #define BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value 452 * than programmed. The exact delta is decided by 453 * driver per chip/boardtype. This can be used 454 * when tempsense qualification happens after shipment 455 */ 456 #define BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */ 457 #define BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */ 458 #define BFL2_EXTLNA_PWRSAVE 0x08000000 /* boardflag to enable ucode to apply power save */ 459 /* ucode control of eLNA during Tx */ 460 #define BFL2_4313_RADIOREG 0x10000000 461 /* board rework */ 462 #define BFL2_DYNAMIC_VMID 0x10000000 /* boardflag to enable dynamic Vmid idle TSSI CAL */ 463 #define BFL2_SDR_EN 0x20000000 /* SDR enabled or disabled */ 464 #define BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */ 465 #define BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */ 466 467 /* SROM 11 - 11ac boardflag definitions */ 468 #define BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */ 469 #define BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */ 470 #define BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ 471 #define BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ 472 #define BFL_SROM11_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ 473 #define BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ 474 #define BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */ 475 #define BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */ 476 477 /* boardflags3 */ 478 #define BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */ 479 #define BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */ 480 #define BFL3_TXGAINTBLID 0x00000070 /* acphy, txgain table id */ 481 #define BFL3_TXGAINTBLID_SHIFT 0x4 /* acphy, txgain table id shift bit */ 482 #define BFL3_TSSI_DIV_WAR 0x00000080 /* acphy, Seperate paparam for 20/40/80 */ 483 #define BFL3_TSSI_DIV_WAR_SHIFT 0x7 /* acphy, Seperate paparam for 20/40/80 shift bit */ 484 #define BFL3_FEMTBL_FROM_NVRAM 0x00000100 /* acphy, femctrl table is read from nvram */ 485 #define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 /* acphy, femctrl table is read from nvram */ 486 #define BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */ 487 #define BFL3_AGC_CFG_5G 0x00000400 /* acphy, gain control configuration for 5G */ 488 #define BFL3_PPR_BIT_EXT 0x00000800 /* acphy, bit position for 1bit extension for ppr */ 489 #define BFL3_PPR_BIT_EXT_SHIFT 11 /* acphy, bit shift for 1bit extension for ppr */ 490 #define BFL3_BBPLL_SPR_MODE_DIS 0x00001000 /* acphy, disables bbpll spur modes */ 491 #define BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */ 492 #define BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */ 493 #define BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */ 494 #define BFL3_5GTXGAINTBL_BLANK 0x00008000 /* acphy, blank the first X ticks of 5g gaintbl */ 495 #define BFL3_5GTXGAINTBL_BLANK_SHIFT 15 /* acphy, blank the first X ticks of 5g gaintbl */ 496 #define BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ 497 #define BFL3_PHASETRACK_MAX_ALPHABETA 0x00010000 /* acphy, to max out alpha,beta to 511 */ 498 #define BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16 /* acphy, to max out alpha,beta to 511 */ 499 #define BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ 500 #define BFL3_EN_NONBRCM_TXBF 0x10000000 /* acphy, enable non-brcm TXBF */ 501 #define BFL3_EN_P2PLINK_TXBF 0x20000000 /* acphy, enable TXBF in p2p links */ 502 503 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ 504 #define BOARD_GPIO_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */ 505 #define BOARD_GPIO_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */ 506 #define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */ 507 #define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */ 508 #define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */ 509 #define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */ 510 #define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ 511 #define BOARD_GPIO_12 0x1000 /* gpio 12 */ 512 #define BOARD_GPIO_13 0x2000 /* gpio 13 */ 513 #define BOARD_GPIO_BTC4_IN 0x0800 /* gpio 11, coex4, in */ 514 #define BOARD_GPIO_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */ 515 #define BOARD_GPIO_BTC4_STAT 0x4000 /* gpio 14, coex4, status */ 516 #define BOARD_GPIO_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */ 517 #define BOARD_GPIO_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */ 518 #define BOARD_GPIO_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */ 519 #define BOARD_GPIO_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */ 520 521 #define GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */ 522 #define GPIO_BTC4W_OUT_43224 0x020 /* bit 5 is BT_IODISABLE */ 523 #define GPIO_BTC4W_OUT_43224_SHARED 0x0e0 /* bit 5 is BT_IODISABLE */ 524 #define GPIO_BTC4W_OUT_43225 0x0e0 /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */ 525 #define GPIO_BTC4W_OUT_43421 0x020 /* bit 5 is BT_IODISABLE */ 526 #define GPIO_BTC4W_OUT_4313 0x060 /* bit 5 SW_BT, bit 6 SW_WL */ 527 #define GPIO_BTC4W_OUT_4331_SHARED 0x010 /* GPIO 4 */ 528 529 #define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ 530 #define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ 531 #define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */ 532 #define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */ 533 534 /* power control defines */ 535 #define PLL_DELAY 150 /* us pll on delay */ 536 #define FREF_DELAY 200 /* us fref change delay */ 537 #define MIN_SLOW_CLK 32 /* us Slow clock period */ 538 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ 539 540 541 /* 43341 Boards */ 542 #define BCM943341WLABGS_SSID 0x062d 543 544 /* 43342 Boards */ 545 #define BCM943342FCAGBI_SSID 0x0641 546 547 /* # of GPIO pins */ 548 #define GPIO_NUMPINS 32 549 550 /* These values are used by dhd host driver. */ 551 #define RDL_RAM_BASE_4319 0x60000000 552 #define RDL_RAM_BASE_4329 0x60000000 553 #define RDL_RAM_SIZE_4319 0x48000 554 #define RDL_RAM_SIZE_4329 0x48000 555 #define RDL_RAM_SIZE_43236 0x70000 556 #define RDL_RAM_BASE_43236 0x60000000 557 #define RDL_RAM_SIZE_4328 0x60000 558 #define RDL_RAM_BASE_4328 0x80000000 559 #define RDL_RAM_SIZE_4322 0x60000 560 #define RDL_RAM_BASE_4322 0x60000000 561 #define RDL_RAM_SIZE_4360 0xA0000 562 #define RDL_RAM_BASE_4360 0x60000000 563 #define RDL_RAM_SIZE_43242 0x90000 564 #define RDL_RAM_BASE_43242 0x60000000 565 #define RDL_RAM_SIZE_43143 0x70000 566 #define RDL_RAM_BASE_43143 0x60000000 567 #define RDL_RAM_SIZE_4350 0xC0000 568 #define RDL_RAM_BASE_4350 0x180800 569 570 /* generic defs for nvram "muxenab" bits 571 * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options. 572 */ 573 #define MUXENAB_UART 0x00000001 574 #define MUXENAB_GPIO 0x00000002 575 #define MUXENAB_ERCX 0x00000004 /* External Radio BT coex */ 576 #define MUXENAB_JTAG 0x00000008 577 #define MUXENAB_HOST_WAKE 0x00000010 /* configure GPIO for SDIO host_wake */ 578 #define MUXENAB_I2S_EN 0x00000020 579 #define MUXENAB_I2S_MASTER 0x00000040 580 #define MUXENAB_I2S_FULL 0x00000080 581 #define MUXENAB_SFLASH 0x00000100 582 #define MUXENAB_RFSWCTRL0 0x00000200 583 #define MUXENAB_RFSWCTRL1 0x00000400 584 #define MUXENAB_RFSWCTRL2 0x00000800 585 #define MUXENAB_SECI 0x00001000 586 #define MUXENAB_BT_LEGACY 0x00002000 587 #define MUXENAB_HOST_WAKE1 0x00004000 /* configure alternative GPIO for SDIO host_wake */ 588 589 /* Boot flags */ 590 #define FLASH_KERNEL_NFLASH 0x00000001 591 #define FLASH_BOOT_NFLASH 0x00000002 592 593 #endif /* _BCMDEVS_H */ 594