/system/core/libpixelflinger/codeflinger/ |
D | load_store.cpp | 84 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 8)); in load() 86 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 16)); in load() 91 ORR(AL, 0, s1, s1, reg_imm(s0, LSL, 8)); in load() 93 ORR(AL, 0, s.reg, s1, reg_imm(s0, LSL, 16)); in load() 127 MOV(AL, 0, d.reg, reg_imm(s, LSL, 32-h)); in extract() 202 RSB(AL, 0, d, s, reg_imm(s, LSL, dbits)); in expand() 208 MOV(AL, 0, d, reg_imm(s, LSL, dbits-sbits)); in expand() 222 ORR(AL, 0, d, s, reg_imm(s, LSL, sbits)); in expand() 299 MOV(AL, 0, ireg, reg_imm(s.reg, LSL, 32-sh)); in downshift() 337 else if (shift<0) ADD(AL, 0, ireg, ireg, reg_imm(dither.reg, LSL,-shift)); in downshift() [all …]
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D | GGLAssembler.cpp | 378 ADD(AL, 0, tx, tx, reg_imm(ty, LSL, GGL_DITHER_ORDER_SHIFT)); in build_scanline_prolog() 379 ORR(AL, 0, parts.count.reg, tx, reg_imm(parts.count.reg, LSL, 16)); in build_scanline_prolog() 383 MOV(AL, 0, parts.count.reg, reg_imm(parts.count.reg, LSL, 16)); in build_scanline_prolog() 432 ADDR_ADD(AL, 0, zbase, zbase, reg_imm(Rs, LSL, 1)); in build_scanline_prolog() 447 ADDR_ADD(AL, 0, parts.covPtr.reg, parts.covPtr.reg, reg_imm(Rx, LSL, 1)); in build_scanline_prolog() 686 MOV(AL, 0, fragment.reg, reg_imm(incoming.reg, LSL, 1)); in build_coverage_application() 996 ADDR_ADD(AL, 0, d.reg, b.reg, reg_imm(o.reg, LSL, 2)); in base_offset() 1000 ADDR_ADD(AL, 0, d.reg, b.reg, reg_imm(o.reg, LSL, 1)); in base_offset() 1003 ADDR_ADD(AL, 0, d.reg, o.reg, reg_imm(o.reg, LSL, 1)); in base_offset() 1008 ADDR_ADD(AL, 0, d.reg, b.reg, reg_imm(o.reg, LSL, 1)); in base_offset()
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D | texturing.cpp | 533 MOV(GE, 0, width, reg_imm(width, LSL, shift)); in build_textures() 550 MOV(LE, 0, u, reg_imm(width, LSL, FRAC_BITS)); in build_textures() 568 MOV(GE, 0, height, reg_imm(height, LSL, shift)); in build_textures() 574 MOV(LE, 0, v, reg_imm(height, LSL, FRAC_BITS)); in build_textures() 577 MOV(GT, 0, height, reg_imm(stride, LSL, shift)); in build_textures() 823 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift)); in filter16() 838 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift)); in filter16() 852 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift)); in filter16() 865 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift)); in filter16() 964 AND(AL, 0, dl, dl, reg_imm(mask, LSL, 8)); in filter32() [all …]
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D | blending.cpp | 450 else if (shift<0) RSB(AL, 0, diff.reg, fb.reg, reg_imm(fragment.reg, LSL,-shift)); in build_blendFOneMinusF() 468 else if (shift<0) SUB(AL, 0, diff.reg, fb.reg, reg_imm(fragment.reg, LSL,-shift)); in build_blendOneMinusFF() 621 ADD(AL, 0, d.reg, temp, reg_imm(add.reg, LSL, ms-as)); in mul_factor_add() 645 ADD(AL, 0, d.reg, src.reg, reg_imm(dst.reg, LSL, shift)); in component_add()
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D | MIPS64Assembler.cpp | 376 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break; in dataProcAdrModes() 499 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing() 526 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing()
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D | ARMAssemblerInterface.h | 43 LSL, LSR, ASR, ROR enumerator
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D | MIPSAssembler.cpp | 391 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break; in dataProcAdrModes() 502 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing() 534 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing()
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D | Arm64Assembler.cpp | 469 if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_type == LSL) in ADDR_ADD()
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