1 /*
2 * Copyright (C) 2017 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <stdint.h>
18
19 #include <gtest/gtest.h>
20
21 #include <unwindstack/Elf.h>
22 #include <unwindstack/ElfInterface.h>
23 #include <unwindstack/MapInfo.h>
24 #include <unwindstack/RegsArm.h>
25 #include <unwindstack/RegsArm64.h>
26 #include <unwindstack/RegsX86.h>
27 #include <unwindstack/RegsX86_64.h>
28 #include <unwindstack/RegsMips.h>
29 #include <unwindstack/RegsMips64.h>
30
31 #include "ElfFake.h"
32 #include "MemoryFake.h"
33 #include "RegsFake.h"
34
35 namespace unwindstack {
36
37 class RegsTest : public ::testing::Test {
38 protected:
SetUp()39 void SetUp() override {
40 memory_ = new MemoryFake;
41 elf_.reset(new ElfFake(memory_));
42 elf_interface_ = new ElfInterfaceFake(elf_->memory());
43 elf_->FakeSetInterface(elf_interface_);
44 }
45
46 ElfInterfaceFake* elf_interface_;
47 MemoryFake* memory_;
48 std::unique_ptr<ElfFake> elf_;
49 };
50
TEST_F(RegsTest,regs32)51 TEST_F(RegsTest, regs32) {
52 RegsImplFake<uint32_t> regs32(50);
53 ASSERT_EQ(50U, regs32.total_regs());
54
55 uint32_t* raw = reinterpret_cast<uint32_t*>(regs32.RawData());
56 for (size_t i = 0; i < 50; i++) {
57 raw[i] = 0xf0000000 + i;
58 }
59 regs32.set_pc(0xf0120340);
60 regs32.set_sp(0xa0ab0cd0);
61
62 for (size_t i = 0; i < 50; i++) {
63 ASSERT_EQ(0xf0000000U + i, regs32[i]) << "Failed comparing register " << i;
64 }
65
66 ASSERT_EQ(0xf0120340U, regs32.pc());
67 ASSERT_EQ(0xa0ab0cd0U, regs32.sp());
68
69 regs32[32] = 10;
70 ASSERT_EQ(10U, regs32[32]);
71 }
72
TEST_F(RegsTest,regs64)73 TEST_F(RegsTest, regs64) {
74 RegsImplFake<uint64_t> regs64(30);
75 ASSERT_EQ(30U, regs64.total_regs());
76
77 uint64_t* raw = reinterpret_cast<uint64_t*>(regs64.RawData());
78 for (size_t i = 0; i < 30; i++) {
79 raw[i] = 0xf123456780000000UL + i;
80 }
81 regs64.set_pc(0xf123456780102030UL);
82 regs64.set_sp(0xa123456780a0b0c0UL);
83
84 for (size_t i = 0; i < 30; i++) {
85 ASSERT_EQ(0xf123456780000000U + i, regs64[i]) << "Failed reading register " << i;
86 }
87
88 ASSERT_EQ(0xf123456780102030UL, regs64.pc());
89 ASSERT_EQ(0xa123456780a0b0c0UL, regs64.sp());
90
91 regs64[8] = 10;
92 ASSERT_EQ(10U, regs64[8]);
93 }
94
TEST_F(RegsTest,rel_pc)95 TEST_F(RegsTest, rel_pc) {
96 RegsArm64 arm64;
97 EXPECT_EQ(4U, arm64.GetPcAdjustment(0x10, elf_.get()));
98 EXPECT_EQ(4U, arm64.GetPcAdjustment(0x4, elf_.get()));
99 EXPECT_EQ(0U, arm64.GetPcAdjustment(0x3, elf_.get()));
100 EXPECT_EQ(0U, arm64.GetPcAdjustment(0x2, elf_.get()));
101 EXPECT_EQ(0U, arm64.GetPcAdjustment(0x1, elf_.get()));
102 EXPECT_EQ(0U, arm64.GetPcAdjustment(0x0, elf_.get()));
103
104 RegsX86 x86;
105 EXPECT_EQ(1U, x86.GetPcAdjustment(0x100, elf_.get()));
106 EXPECT_EQ(1U, x86.GetPcAdjustment(0x2, elf_.get()));
107 EXPECT_EQ(1U, x86.GetPcAdjustment(0x1, elf_.get()));
108 EXPECT_EQ(0U, x86.GetPcAdjustment(0x0, elf_.get()));
109
110 RegsX86_64 x86_64;
111 EXPECT_EQ(1U, x86_64.GetPcAdjustment(0x100, elf_.get()));
112 EXPECT_EQ(1U, x86_64.GetPcAdjustment(0x2, elf_.get()));
113 EXPECT_EQ(1U, x86_64.GetPcAdjustment(0x1, elf_.get()));
114 EXPECT_EQ(0U, x86_64.GetPcAdjustment(0x0, elf_.get()));
115
116 RegsMips mips;
117 EXPECT_EQ(8U, mips.GetPcAdjustment(0x10, elf_.get()));
118 EXPECT_EQ(8U, mips.GetPcAdjustment(0x8, elf_.get()));
119 EXPECT_EQ(0U, mips.GetPcAdjustment(0x7, elf_.get()));
120 EXPECT_EQ(0U, mips.GetPcAdjustment(0x6, elf_.get()));
121 EXPECT_EQ(0U, mips.GetPcAdjustment(0x5, elf_.get()));
122 EXPECT_EQ(0U, mips.GetPcAdjustment(0x4, elf_.get()));
123 EXPECT_EQ(0U, mips.GetPcAdjustment(0x3, elf_.get()));
124 EXPECT_EQ(0U, mips.GetPcAdjustment(0x2, elf_.get()));
125 EXPECT_EQ(0U, mips.GetPcAdjustment(0x1, elf_.get()));
126 EXPECT_EQ(0U, mips.GetPcAdjustment(0x0, elf_.get()));
127
128 RegsMips64 mips64;
129 EXPECT_EQ(8U, mips64.GetPcAdjustment(0x10, elf_.get()));
130 EXPECT_EQ(8U, mips64.GetPcAdjustment(0x8, elf_.get()));
131 EXPECT_EQ(0U, mips64.GetPcAdjustment(0x7, elf_.get()));
132 EXPECT_EQ(0U, mips64.GetPcAdjustment(0x6, elf_.get()));
133 EXPECT_EQ(0U, mips64.GetPcAdjustment(0x5, elf_.get()));
134 EXPECT_EQ(0U, mips64.GetPcAdjustment(0x4, elf_.get()));
135 EXPECT_EQ(0U, mips64.GetPcAdjustment(0x3, elf_.get()));
136 EXPECT_EQ(0U, mips64.GetPcAdjustment(0x2, elf_.get()));
137 EXPECT_EQ(0U, mips64.GetPcAdjustment(0x1, elf_.get()));
138 EXPECT_EQ(0U, mips64.GetPcAdjustment(0x0, elf_.get()));
139 }
140
TEST_F(RegsTest,rel_pc_arm)141 TEST_F(RegsTest, rel_pc_arm) {
142 RegsArm arm;
143
144 // Check fence posts.
145 elf_->FakeSetLoadBias(0);
146 EXPECT_EQ(2U, arm.GetPcAdjustment(0x5, elf_.get()));
147 EXPECT_EQ(2U, arm.GetPcAdjustment(0x4, elf_.get()));
148 EXPECT_EQ(2U, arm.GetPcAdjustment(0x3, elf_.get()));
149 EXPECT_EQ(2U, arm.GetPcAdjustment(0x2, elf_.get()));
150 EXPECT_EQ(0U, arm.GetPcAdjustment(0x1, elf_.get()));
151 EXPECT_EQ(0U, arm.GetPcAdjustment(0x0, elf_.get()));
152
153 elf_->FakeSetLoadBias(0x100);
154 EXPECT_EQ(0U, arm.GetPcAdjustment(0x1, elf_.get()));
155 EXPECT_EQ(2U, arm.GetPcAdjustment(0x2, elf_.get()));
156 EXPECT_EQ(2U, arm.GetPcAdjustment(0xff, elf_.get()));
157 EXPECT_EQ(2U, arm.GetPcAdjustment(0x105, elf_.get()));
158 EXPECT_EQ(2U, arm.GetPcAdjustment(0x104, elf_.get()));
159 EXPECT_EQ(2U, arm.GetPcAdjustment(0x103, elf_.get()));
160 EXPECT_EQ(2U, arm.GetPcAdjustment(0x102, elf_.get()));
161 EXPECT_EQ(0U, arm.GetPcAdjustment(0x101, elf_.get()));
162 EXPECT_EQ(0U, arm.GetPcAdjustment(0x100, elf_.get()));
163
164 // Check thumb instructions handling.
165 elf_->FakeSetLoadBias(0);
166 memory_->SetData32(0x2000, 0);
167 EXPECT_EQ(2U, arm.GetPcAdjustment(0x2005, elf_.get()));
168 memory_->SetData32(0x2000, 0xe000f000);
169 EXPECT_EQ(4U, arm.GetPcAdjustment(0x2005, elf_.get()));
170
171 elf_->FakeSetLoadBias(0x400);
172 memory_->SetData32(0x2100, 0);
173 EXPECT_EQ(2U, arm.GetPcAdjustment(0x2505, elf_.get()));
174 memory_->SetData32(0x2100, 0xf111f111);
175 EXPECT_EQ(4U, arm.GetPcAdjustment(0x2505, elf_.get()));
176 }
177
TEST_F(RegsTest,elf_invalid)178 TEST_F(RegsTest, elf_invalid) {
179 RegsArm regs_arm;
180 RegsArm64 regs_arm64;
181 RegsX86 regs_x86;
182 RegsX86_64 regs_x86_64;
183 RegsMips regs_mips;
184 RegsMips64 regs_mips64;
185 MapInfo map_info(nullptr, 0x1000, 0x2000, 0, 0, "");
186 Elf* invalid_elf = new Elf(nullptr);
187 map_info.elf.reset(invalid_elf);
188
189 regs_arm.set_pc(0x1500);
190 EXPECT_EQ(0x500U, invalid_elf->GetRelPc(regs_arm.pc(), &map_info));
191 EXPECT_EQ(2U, regs_arm.GetPcAdjustment(0x500U, invalid_elf));
192 EXPECT_EQ(2U, regs_arm.GetPcAdjustment(0x511U, invalid_elf));
193
194 regs_arm64.set_pc(0x1600);
195 EXPECT_EQ(0x600U, invalid_elf->GetRelPc(regs_arm64.pc(), &map_info));
196 EXPECT_EQ(4U, regs_arm64.GetPcAdjustment(0x600U, invalid_elf));
197
198 regs_x86.set_pc(0x1700);
199 EXPECT_EQ(0x700U, invalid_elf->GetRelPc(regs_x86.pc(), &map_info));
200 EXPECT_EQ(1U, regs_x86.GetPcAdjustment(0x700U, invalid_elf));
201
202 regs_x86_64.set_pc(0x1800);
203 EXPECT_EQ(0x800U, invalid_elf->GetRelPc(regs_x86_64.pc(), &map_info));
204 EXPECT_EQ(1U, regs_x86_64.GetPcAdjustment(0x800U, invalid_elf));
205
206 regs_mips.set_pc(0x1900);
207 EXPECT_EQ(0x900U, invalid_elf->GetRelPc(regs_mips.pc(), &map_info));
208 EXPECT_EQ(8U, regs_mips.GetPcAdjustment(0x900U, invalid_elf));
209
210 regs_mips64.set_pc(0x1a00);
211 EXPECT_EQ(0xa00U, invalid_elf->GetRelPc(regs_mips64.pc(), &map_info));
212 EXPECT_EQ(8U, regs_mips64.GetPcAdjustment(0xa00U, invalid_elf));
213 }
214
TEST_F(RegsTest,arm_verify_sp_pc)215 TEST_F(RegsTest, arm_verify_sp_pc) {
216 RegsArm arm;
217 uint32_t* regs = reinterpret_cast<uint32_t*>(arm.RawData());
218 regs[13] = 0x100;
219 regs[15] = 0x200;
220 EXPECT_EQ(0x100U, arm.sp());
221 EXPECT_EQ(0x200U, arm.pc());
222 }
223
TEST_F(RegsTest,arm64_verify_sp_pc)224 TEST_F(RegsTest, arm64_verify_sp_pc) {
225 RegsArm64 arm64;
226 uint64_t* regs = reinterpret_cast<uint64_t*>(arm64.RawData());
227 regs[31] = 0xb100000000ULL;
228 regs[32] = 0xc200000000ULL;
229 EXPECT_EQ(0xb100000000U, arm64.sp());
230 EXPECT_EQ(0xc200000000U, arm64.pc());
231 }
232
TEST_F(RegsTest,x86_verify_sp_pc)233 TEST_F(RegsTest, x86_verify_sp_pc) {
234 RegsX86 x86;
235 uint32_t* regs = reinterpret_cast<uint32_t*>(x86.RawData());
236 regs[4] = 0x23450000;
237 regs[8] = 0xabcd0000;
238 EXPECT_EQ(0x23450000U, x86.sp());
239 EXPECT_EQ(0xabcd0000U, x86.pc());
240 }
241
TEST_F(RegsTest,x86_64_verify_sp_pc)242 TEST_F(RegsTest, x86_64_verify_sp_pc) {
243 RegsX86_64 x86_64;
244 uint64_t* regs = reinterpret_cast<uint64_t*>(x86_64.RawData());
245 regs[7] = 0x1200000000ULL;
246 regs[16] = 0x4900000000ULL;
247 EXPECT_EQ(0x1200000000U, x86_64.sp());
248 EXPECT_EQ(0x4900000000U, x86_64.pc());
249 }
250
TEST_F(RegsTest,mips_verify_sp_pc)251 TEST_F(RegsTest, mips_verify_sp_pc) {
252 RegsMips mips;
253 uint32_t* regs = reinterpret_cast<uint32_t*>(mips.RawData());
254 regs[29] = 0x100;
255 regs[32] = 0x200;
256 EXPECT_EQ(0x100U, mips.sp());
257 EXPECT_EQ(0x200U, mips.pc());
258 }
259
TEST_F(RegsTest,mips64_verify_sp_pc)260 TEST_F(RegsTest, mips64_verify_sp_pc) {
261 RegsMips64 mips64;
262 uint64_t* regs = reinterpret_cast<uint64_t*>(mips64.RawData());
263 regs[29] = 0xb100000000ULL;
264 regs[32] = 0xc200000000ULL;
265 EXPECT_EQ(0xb100000000U, mips64.sp());
266 EXPECT_EQ(0xc200000000U, mips64.pc());
267 }
268
TEST_F(RegsTest,machine_type)269 TEST_F(RegsTest, machine_type) {
270 RegsArm arm_regs;
271 EXPECT_EQ(ARCH_ARM, arm_regs.Arch());
272
273 RegsArm64 arm64_regs;
274 EXPECT_EQ(ARCH_ARM64, arm64_regs.Arch());
275
276 RegsX86 x86_regs;
277 EXPECT_EQ(ARCH_X86, x86_regs.Arch());
278
279 RegsX86_64 x86_64_regs;
280 EXPECT_EQ(ARCH_X86_64, x86_64_regs.Arch());
281
282 RegsMips mips_regs;
283 EXPECT_EQ(ARCH_MIPS, mips_regs.Arch());
284
285 RegsMips64 mips64_regs;
286 EXPECT_EQ(ARCH_MIPS64, mips64_regs.Arch());
287 }
288
289 template <typename RegisterType>
clone_test(Regs * regs)290 void clone_test(Regs* regs) {
291 RegisterType* register_values = reinterpret_cast<RegisterType*>(regs->RawData());
292 int num_regs = regs->total_regs();
293 for (int i = 0; i < num_regs; ++i) {
294 register_values[i] = i;
295 }
296
297 std::unique_ptr<Regs> clone(regs->Clone());
298 ASSERT_EQ(regs->total_regs(), clone->total_regs());
299 RegisterType* clone_values = reinterpret_cast<RegisterType*>(clone->RawData());
300 for (int i = 0; i < num_regs; ++i) {
301 EXPECT_EQ(register_values[i], clone_values[i]);
302 EXPECT_NE(®ister_values[i], &clone_values[i]);
303 }
304 }
305
TEST_F(RegsTest,clone)306 TEST_F(RegsTest, clone) {
307 std::vector<std::unique_ptr<Regs>> regs;
308 regs.emplace_back(new RegsArm());
309 regs.emplace_back(new RegsArm64());
310 regs.emplace_back(new RegsX86());
311 regs.emplace_back(new RegsX86_64());
312 regs.emplace_back(new RegsMips());
313 regs.emplace_back(new RegsMips64());
314
315 for (auto& r : regs) {
316 if (r->Is32Bit()) {
317 clone_test<uint32_t>(r.get());
318 } else {
319 clone_test<uint64_t>(r.get());
320 }
321 }
322 }
323
324 } // namespace unwindstack
325