| /external/vixl/examples/aarch64/ |
| D | add4-double.cc | 44 __ Fadd(d0, d0, d1); in GenerateAdd4Double() local
45 __ Fadd(d2, d2, d3); in GenerateAdd4Double() local
46 __ Fadd(d0, d0, d2); in GenerateAdd4Double() local
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| D | add3-double.cc | 37 __ Fadd(d0, d0, d1); // d0 <- x + y in GenerateAdd3Double() local
38 __ Fadd(d0, d0, d2); // d0 <- d0 + z in GenerateAdd3Double() local
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| D | custom-disassembler.cc | 128 __ Fadd(d30, d16, d17); in GenerateCustomDisassemblerTestCode() local
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 10589 __ Fadd(s0, s17, s18); in TEST() local
10590 __ Fadd(s1, s18, s19); in TEST() local
10591 __ Fadd(s2, s14, s18); in TEST() local
10592 __ Fadd(s3, s15, s18); in TEST() local
10593 __ Fadd(s4, s16, s18); in TEST() local
10594 __ Fadd(s5, s15, s16); in TEST() local
10595 __ Fadd(s6, s16, s15); in TEST() local
10597 __ Fadd(d7, d30, d31); in TEST() local
10598 __ Fadd(d8, d29, d31); in TEST() local
10599 __ Fadd(d9, d26, d31); in TEST() local
[all …]
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| D | test-simulator-aarch64.cc | 5002 __ Fadd(temp, temp, input_1.D()); in GenerateSum() local
5003 __ Fadd(result, temp, input_3); in GenerateSum() local
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1305 __ Fadd(i.OutputFloat32Register(), i.InputFloat32Register(0), in AssembleArchInstruction() local
1340 __ Fadd(i.OutputDoubleRegister(), i.InputDoubleRegister(0), in AssembleArchInstruction() local
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 487 void TurboAssembler::Fadd(const VRegister& fd, const VRegister& fn, in Fadd() function
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2595 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); in ExpandLegalINT_TO_FP() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2414 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); in ExpandLegalINT_TO_FP() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2448 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); in ExpandLegalINT_TO_FP() local
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 1323 void Fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) { in Fadd() function
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