Searched defs:Offset0 (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 130 bool SILoadStoreOptimizer::offsetsCanBeCombined(unsigned Offset0, in offsetsCanBeCombined()
181 unsigned Offset0 = I->getOperand(OffsetIdx).getImm() & 0xffff; in findMatchingDSInst() local
205 unsigned Offset0 in mergeRead2Pair() local
301 unsigned Offset0 in mergeWrite2Pair() local
|
| D | AMDGPUInstrInfo.cpp | 51 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear()
|
| D | SIInstrInfo.cpp | 94 int64_t &Offset0, in areLoadsFromSameBasePtr()
231 uint8_t Offset0 = Offset0Imm->getImm(); in getMemOpBaseRegImmOfs() local
1344 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
|
| D | AMDGPUISelDAGToDAG.cpp | 719 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 279 int Offset0; in apply() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 92 unsigned Offset0; member
|
| D | SIInstrInfo.cpp | 151 int64_t &Offset0, in areLoadsFromSameBasePtr()
293 uint8_t Offset0 = Offset0Imm->getImm(); in getMemOpBaseRegImmOfs() local
467 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear()
2121 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
|
| D | AMDGPUISelDAGToDAG.cpp | 905 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 9847 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 12396 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
|