| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 467 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
472 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
476 static inline bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
483 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
487 static inline bool isPopOpcode(int Opc) { in isPopOpcode()
493 static inline bool isPushOpcode(int Opc) { in isPushOpcode()
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| D | ARMFastISel.cpp | 432 unsigned Opc; in ARMMaterializeFP() local
457 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
475 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
491 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
563 unsigned Opc; in ARMMaterializeGV() local
596 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci; in ARMMaterializeGV() local
612 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV() local
677 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in fastMaterializeAlloca() local
855 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
921 unsigned Opc; in ARMEmitLoad() local
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 420 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
425 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
430 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
436 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
440 static inline bool isPopOpcode(int Opc) { in isPopOpcode()
446 static inline bool isPushOpcode(int Opc) { in isPushOpcode()
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| D | ARMISelDAGToDAG.cpp | 112 SDValue &Opc) { in SelectAddrMode2Base()
117 SDValue &Opc) { in SelectAddrMode2ShOp()
122 SDValue &Opc) { in SelectAddrMode2()
308 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate()
533 SDValue &Opc, in SelectImmShifterOperand()
573 SDValue &Opc, in SelectRegShifterOperand()
652 SDValue &Opc) { in SelectLdStSOReg()
763 SDValue &Opc) { in SelectAddrMode2Worker()
900 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetReg()
936 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImmPre()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 258 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode()
260 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
277 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; } in isIndirectBranchOpcode()
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| D | AArch64LoadStoreOptimizer.cpp | 199 static bool isNarrowStore(unsigned Opc) { in isNarrowStore()
211 static bool isNarrowLoad(unsigned Opc) { in isNarrowLoad()
231 static bool isNarrowLoadOrStore(unsigned Opc) { in isNarrowLoadOrStore()
293 static unsigned getMatchingNonSExtOpcode(unsigned Opc, in getMatchingNonSExtOpcode()
346 static unsigned getMatchingWideOpcode(unsigned Opc) { in getMatchingWideOpcode()
377 static unsigned getMatchingPairOpcode(unsigned Opc) { in getMatchingPairOpcode()
447 static unsigned getPreIndexedOpcode(unsigned Opc) { in getPreIndexedOpcode()
506 static unsigned getPostIndexedOpcode(unsigned Opc) { in getPostIndexedOpcode()
617 static bool isPromotableZeroStoreOpcode(unsigned Opc) { in isPromotableZeroStoreOpcode()
643 unsigned Opc = I->getOpcode(); in mergeNarrowInsns() local
[all …]
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| D | AArch64ConditionOptimizer.cpp | 206 static int getComplementOpc(int Opc) { in getComplementOpc()
233 unsigned Opc = CmpMI->getOpcode(); in adjustCmp() local
262 unsigned Opc; in modifyCmp() local
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 51 unsigned Opc = MI->getOpcode(); in isLoadFromStackSlot() local
76 unsigned Opc = MI->getOpcode(); in isStoreToStackSlot() local
106 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
172 unsigned Opc = 0; in storeRegToStackSlot() local
198 unsigned Opc = 0; in loadRegFromStackSlot() local
228 static unsigned GetAnalyzableBrOpc(unsigned Opc) { in GetAnalyzableBrOpc()
239 unsigned Mips::GetOppositeBranchOpc(unsigned Opc) in GetOppositeBranchOpc()
260 static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc, in AnalyzeCondBr()
359 unsigned Opc = Cond[0].getImm(); in BuildCondBr() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 315 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
320 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
325 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
331 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
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| D | ARMISelDAGToDAG.cpp | 120 SDValue &Opc) { in SelectAddrMode2Base()
125 SDValue &Opc) { in SelectAddrMode2ShOp()
130 SDValue &Opc) { in SelectAddrMode2()
307 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate()
392 SDValue &Opc, in SelectImmShifterOperand()
416 SDValue &Opc, in SelectRegShifterOperand()
492 SDValue &Opc) { in SelectLdStSOReg()
592 SDValue &Opc) { in SelectAddrMode2Worker()
725 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetReg()
761 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImmPre()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | ConstantFoldingMIRBuilder.h | 92 MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, UseArg1Ty &&Arg1, in buildInstr()
101 MachineInstrBuilder buildInstr(unsigned Opc, unsigned Dst, unsigned Src0, in buildInstr()
127 MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, in buildInstr()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 324 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode()
326 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
343 static inline bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
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| D | AArch64LoadStoreOptimizer.cpp | 193 static bool isNarrowStore(unsigned Opc) { in isNarrowStore()
263 static unsigned getMatchingNonSExtOpcode(unsigned Opc, in getMatchingNonSExtOpcode()
304 static unsigned getMatchingWideOpcode(unsigned Opc) { in getMatchingWideOpcode()
323 static unsigned getMatchingPairOpcode(unsigned Opc) { in getMatchingPairOpcode()
393 static unsigned getPreIndexedOpcode(unsigned Opc) { in getPreIndexedOpcode()
456 static unsigned getPostIndexedOpcode(unsigned Opc) { in getPostIndexedOpcode()
578 unsigned Opc = MI.getOpcode(); in isPromotableZeroStoreInst() local
603 unsigned Opc = MI.getOpcode(); in isMergeableLdStUpdate() local
669 unsigned Opc = I->getOpcode(); in mergeNarrowZeroStores() local
737 unsigned Opc = in mergePairedInsns() local
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| D | AArch64ConditionOptimizer.cpp | 217 static int getComplementOpc(int Opc) { in getComplementOpc()
244 unsigned Opc = CmpMI->getOpcode(); in adjustCmp() local
273 unsigned Opc; in modifyCmp() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyExplicitLocals.cpp | 245 unsigned Opc = getGetLocalOpcode(RC); in runOnMachineFunction() local
255 unsigned Opc = getTeeLocalOpcode(RC); in runOnMachineFunction() local
281 unsigned Opc = getDropOpcode(RC); in runOnMachineFunction() local
289 unsigned Opc = getSetLocalOpcode(RC); in runOnMachineFunction() local
342 unsigned Opc = getGetLocalOpcode(RC); in runOnMachineFunction() local
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| D | WebAssemblyFastISel.cpp | 380 unsigned Opc = Subtarget->hasAddr64() ? in materializeLoadStoreOperands() local
596 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeAlloca() local
612 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeConstant() local
648 unsigned Opc; in fastLowerArguments() local
741 unsigned Opc; in selectCall() local
872 unsigned Opc; in selectSelect() local
969 unsigned Opc; in selectICmp() local
1037 unsigned Opc; in selectFCmp() local
1134 unsigned Opc; in selectLoad() local
1190 unsigned Opc; in selectStore() local
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 61 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch()
67 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump()
115 int Opc = MI.getOpcode(); in runOnMachineFunction() local
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| D | HexagonGenPredicate.cpp | 118 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm()
164 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
188 unsigned Opc = MI->getOpcode(); in collectPredicateGPR() local
236 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
265 bool HexagonGenPredicate::isScalarCmp(unsigned Opc) { in isScalarCmp()
351 unsigned Opc = MI->getOpcode(); in convertToPredForm() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 62 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch()
77 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump()
129 int Opc = MI.getOpcode(); in runOnMachineFunction() local
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| D | HexagonGenPredicate.cpp | 141 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm()
186 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
209 unsigned Opc = MI->getOpcode(); in collectPredicateGPR() local
255 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
284 bool HexagonGenPredicate::isScalarCmp(unsigned Opc) { in isScalarCmp()
369 unsigned Opc = MI->getOpcode(); in convertToPredForm() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 43 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
65 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
190 unsigned Opc = 0; in storeRegToStack() local
258 unsigned Opc = 0; in loadRegFromStack() local
334 unsigned Opc; in expandPostRAPseudo() local
454 unsigned Opc = ABI.GetPtrAdduOp(); in adjustStackPtr() local
537 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 331 unsigned Opc = Subtarget->hasAddr64() ? in materializeLoadStoreOperands() local
531 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeAlloca() local
547 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeConstant() local
581 unsigned Opc; in fastLowerArguments() local
635 unsigned Opc; in selectCall() local
735 unsigned Opc; in selectSelect() local
822 unsigned Opc; in selectICmp() local
890 unsigned Opc; in selectFCmp() local
982 unsigned Opc; in selectLoad() local
1035 unsigned Opc; in selectStore() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 48 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
70 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
88 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
258 unsigned Opc = 0; in storeRegToStack() local
331 unsigned Opc = 0; in loadRegFromStack() local
412 unsigned Opc; in expandPostRAPseudo() local
590 unsigned Opc = ABI.GetPtrAdduOp(); in adjustStackPtr() local
695 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 1276 unsigned Opc = Orig->getOpcode(); in reMaterialize() local
1336 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() in convertToThreeAddressWithLEA() local
1503 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
1539 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r in convertToThreeAddress() local
1569 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r in convertToThreeAddress() local
1599 unsigned Opc; in convertToThreeAddress() local
1656 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
1704 unsigned Opc; in commuteInstruction() local
1773 unsigned Opc = 0; in commuteInstruction() local
2118 unsigned Opc = GetCondBranchFromCond(CC); in InsertBranch() local
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 51 unsigned Opc = 0; in storeRegToStackSlot() local
81 unsigned Opc = 0; in loadRegFromStackSlot() local
106 unsigned Opc; in copyPhysReg() local
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