| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 213 int RCID = Desc.OpInfo[i].RegClass; in encodeInstruction() local
283 int RCID = Desc.OpInfo[OpNo].RegClass; in getMachineOpValue() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 137 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
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| D | SIInstrInfo.cpp | 3058 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
3079 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
5015 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; in isBufferSMRD() local
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| D | AMDGPUISelDAGToDAG.cpp | 340 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 789 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth()
826 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineInstr.cpp | 879 unsigned RCID; in getRegClassConstraint() local
1475 unsigned RCID = 0; in print() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 344 auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; in convertMIMGInst() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 675 unsigned RCID; in getRegClassConstraint() local
1434 unsigned RCID = 0; in print() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1203 unsigned RCID; in getRegClassConstraint() local
1828 unsigned RCID = 0; in print() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1467 unsigned RCID; in handleSpecialFP() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1515 unsigned RCID; in handleSpecialFP() local
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| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 386 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1860 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
1881 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
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| D | AMDGPUISelDAGToDAG.cpp | 207 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 567 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 343 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods()
1790 int RCID = getRegClass(RegKind, RegWidth); in ParseAMDGPURegister() local
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 932 int RCID = getRegClass(RegKind, RegWidth); in ParseAMDGPURegister() local
|