| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 456 bool isSubRegister(unsigned RegA, unsigned RegB) const { in isSubRegister()
464 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { in isSubRegisterEq()
470 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { in isSuperRegisterEq()
476 bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const { in isSuperOrSubRegisterEq()
552 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ in isSuperRegister()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 434 bool isSubRegister(unsigned RegA, unsigned RegB) const { in isSubRegister()
442 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { in isSubRegisterEq()
448 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { in isSuperRegisterEq()
454 bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const { in isSuperOrSubRegisterEq()
527 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ in isSuperRegister()
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 534 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible()
664 unsigned RegA = MI->getOperand(0).getReg(); in commuteInstruction() local
674 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ in isProfitableToConv3Addr()
693 unsigned RegA, unsigned RegB, in convertInstTo3Addr()
1463 unsigned RegA = DstMO.getReg(); in processTiedPairs() local
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| D | TargetInstrInfo.cpp | 701 unsigned RegA = OpA.getReg(); in reassociateOps() local
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| /external/llvm/lib/Target/X86/ |
| D | X86WinAllocaExpander.cpp | 214 unsigned RegA = (SlotSize == 8) ? X86::RAX : X86::EAX; in lower() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86WinAllocaExpander.cpp | 215 unsigned RegA = (SlotSize == 8) ? X86::RAX : X86::EAX; in lower() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 563 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible()
704 unsigned RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction() local
714 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ in isProfitableToConv3Addr()
733 unsigned RegA, unsigned RegB, in convertInstTo3Addr()
1518 unsigned RegA = DstMO.getReg(); in processTiedPairs() local
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| D | ImplicitNullChecks.cpp | 279 unsigned RegA = MOA.getReg(); in canReorder() local
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| D | TargetInstrInfo.cpp | 811 unsigned RegA = OpA.getReg(); in reassociateOps() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 516 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible()
621 unsigned RegA = MI->getOperand(0).getReg(); in CommuteInstruction() local
631 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ in isProfitableToConv3Addr()
651 unsigned RegA, unsigned RegB, in ConvertInstTo3Addr()
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| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/Analysis/ |
| D | SparsePropagation.cpp | 482 auto RegA = TestLatticeKey(A, IPOGrouping::Register); in TEST_F() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1980 for (auto &RegA : DefsA) in isDependent() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 2047 for (auto &RegA : DefsA) in isDependent() local
|