| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegisterPressure.cpp | 140 void RegPressureTracker::increaseRegPressure(unsigned RegUnit, in increaseRegPressure()
155 void RegPressureTracker::decreaseRegPressure(unsigned RegUnit, in decreaseRegPressure()
348 unsigned RegUnit = Pair.RegUnit; in initLiveThru() local
357 unsigned RegUnit) { in getRegLanes()
368 unsigned RegUnit = Pair.RegUnit; in addRegLanes() local
381 unsigned RegUnit) { in setRegZero()
394 unsigned RegUnit = Pair.RegUnit; in removeRegLanes() local
407 const MachineRegisterInfo &MRI, bool TrackLaneMasks, unsigned RegUnit, in getLanesWithProperty()
436 bool TrackLaneMasks, unsigned RegUnit, in getLiveLanesAt()
593 unsigned RegUnit = I->RegUnit; in adjustLaneLiveness() local
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| D | LiveRegMatrix.cpp | 179 unsigned RegUnit) { in query()
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| /external/llvm/lib/CodeGen/ |
| D | RegisterPressure.cpp | 112 void RegPressureTracker::increaseRegPressure(unsigned RegUnit, in increaseRegPressure()
127 void RegPressureTracker::decreaseRegPressure(unsigned RegUnit, in decreaseRegPressure()
322 unsigned RegUnit = Pair.RegUnit; in initLiveThru() local
330 unsigned RegUnit) { in getRegLanes()
342 unsigned RegUnit = Pair.RegUnit; in addRegLanes() local
356 unsigned RegUnit) { in setRegZero()
370 unsigned RegUnit = Pair.RegUnit; in removeRegLanes() local
384 const MachineRegisterInfo &MRI, bool TrackLaneMasks, unsigned RegUnit, in getLanesWithProperty()
412 bool TrackLaneMasks, unsigned RegUnit, in getLiveLanesAt()
568 unsigned RegUnit = I->RegUnit; in adjustLaneLiveness() local
[all …]
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| D | LiveRegMatrix.cpp | 172 unsigned RegUnit) { in query()
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| D | MachineTraceMetrics.cpp | 681 unsigned RegUnit; member
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 472 struct RegUnit { struct
478 // Each native RegUnit corresponds to one or two root registers. The full argument
490 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { in RegUnit() function
500 // Each RegUnitSet is a sorted vector with a name. argument
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 435 struct RegUnit { struct
441 // Each native RegUnit corresponds to one or two root registers. The full argument
450 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { in RegUnit() function
460 // Each RegUnitSet is a sorted vector with a name. argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | RegisterPressure.h | 41 unsigned RegUnit; ///< Virtual register or register unit. member
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| D | MachineTraceMetrics.h | 77 unsigned RegUnit; member
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| D | MachineRegisterInfo.h | 1158 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator()
1188 getPressureSets(unsigned RegUnit) const { in getPressureSets()
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| D | TargetRegisterInfo.h | 440 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { in hasRegUnit()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterPressure.h | 30 unsigned RegUnit; ///< Virtual register or register unit. member
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| D | MachineRegisterInfo.h | 1029 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator()
1058 getPressureSets(unsigned RegUnit) const { in getPressureSets()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 648 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIWholeQuadMode.cpp | 283 for (MCRegUnitIterator RegUnit(Reg, TRI); RegUnit.isValid(); ++RegUnit) { in markInstructionUses() local
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 617 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 429 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { in hasRegUnit()
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