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Searched defs:pll_rate (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rv1108.c89 ulong pll_rate; in rv1108_mac_set_clk() local
114 u32 pll_rate; in rv1108_sfc_set_clk() local
Dclk_rk3368.c160 u32 pll_rate; in rk3368_mmc_get_clk() local
325 ulong pll_rate; in rk3368_gmac_set_clk() local
Dclk_rk322x.c252 ulong pll_rate; in rk322x_mac_set_clk() local
Dclk_rk3288.c310 ulong pll_rate; in rockchip_mac_set_clk() local
Dclk_rk3328.c419 ulong pll_rate; in rk3328_gmac2io_set_clk() local
/external/u-boot/drivers/clk/
Dclk-hsdk-cgu.c136 const u32 pll_rate[MAX_TUN_CLOCKS]; member
156 const u32 pll_rate[MAX_AXI_CLOCKS]; member
538 ulong pll_rate; in axi_clk_set() local
576 ulong pll_rate; in tun_clk_set() local
Dclk_zynq.c288 ulong pll_rate, in zynq_clk_calc_peripheral_two_divs()
319 ulong pll_rate, new_rate; in zynq_clk_set_peripheral_rate() local
Dclk_zynqmp.c492 ulong pll_rate, in zynqmp_clk_calc_peripheral_two_divs()
523 ulong pll_rate, new_rate; in zynqmp_clk_set_peripheral_rate() local
/external/u-boot/arch/arm/mach-tegra/
Dclock.c25 static unsigned pll_rate[CLOCK_ID_COUNT]; variable