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Searched refs:OutputRegister (Results 1 – 8 of 8) sorted by relevance

/art/compiler/optimizing/
Dintrinsics_arm_vixl.cc50 using helpers::OutputRegister;
467 vixl32::Register out_reg = OutputRegister(invoke); in VisitMathRoundFloat()
510 __ Ldrsb(OutputRegister(invoke), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPeekByte()
520 __ Ldr(OutputRegister(invoke), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPeekIntNative()
551 __ Ldrsh(OutputRegister(invoke), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPeekShortNative()
610 __ Ldr(OutputRegister(invoke), in VisitThreadCurrentThread()
1040 vixl32::Register out = OutputRegister(invoke); // Boolean result. in GenCas()
1180 const vixl32::Register out = OutputRegister(invoke); in VisitStringCompareTo()
1277 const vixl32::Register out = OutputRegister(invoke); in GenerateStringCompareToLoop()
1499 vixl32::Register out = OutputRegister(invoke); in VisitStringEquals()
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Dcode_generator_arm_vixl.cc65 using helpers::OutputRegister;
1525 const vixl32::Register out = OutputRegister(cond); in GenerateConditionGeneric()
1556 const vixl32::Register out = OutputRegister(cond); in GenerateEqualLong()
1612 const vixl32::Register out = OutputRegister(cond); in GenerateConditionLong()
1684 const vixl32::Register out = OutputRegister(cond); in GenerateConditionIntegralOrNonPrimitive()
2643 OutputRegister(flag), in VisitShouldDeoptimizeFlag()
2939 const vixl32::Register out = OutputRegister(cond); in HandleCondition()
3336 __ Rsb(OutputRegister(neg), InputRegisterAt(neg, 0), 0); in VisitNeg()
3530 __ Ubfx(OutputRegister(conversion), InputRegisterAt(conversion, 0), 0, 8); in VisitTypeConversion()
3533 __ Ubfx(OutputRegister(conversion), LowRegisterFrom(in), 0, 8); in VisitTypeConversion()
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Dcode_generator_arm64.cc77 using helpers::OutputRegister;
1975 Register dst = OutputRegister(instr); in HandleBinaryOp()
2054 Register dst = OutputRegister(instr); in HandleShift()
2111 Register dst = OutputRegister(instr); in VisitBitwiseNegatedRight()
2150 Register out = OutputRegister(instruction); in VisitDataProcWithShifterOp()
2213 __ Add(OutputRegister(instruction), in VisitIntermediateAddress()
2243 __ Add(OutputRegister(instruction), index_reg, offset); in VisitIntermediateAddressIndex()
2246 __ Add(OutputRegister(instruction), offset_reg, Operand(index_reg, LSL, shift)); in VisitIntermediateAddressIndex()
2268 Register res = OutputRegister(instr); in VisitMultiplyAccumulate()
2484 vixl::aarch64::Register out = OutputRegister(instruction); in VisitArrayLength()
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Dcommon_arm64.h81 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { in OutputRegister() function
133 : static_cast<vixl::aarch64::CPURegister>(OutputRegister(instr)); in OutputCPURegister()
Dcommon_arm.h144 inline vixl::aarch32::Register OutputRegister(HInstruction* instr) { in OutputRegister() function
Dcode_generator_vector_arm_vixl.cc31 using helpers::OutputRegister;
98 __ Vmov(OutputRegister(instruction), DRegisterLane(src, 0)); in VisitVecExtractScalar()
Dcode_generator_vector_arm64.cc34 using helpers::OutputRegister;
173 __ Umov(OutputRegister(instruction), src.V4S(), 0); in VisitVecExtractScalar()
177 __ Umov(OutputRegister(instruction), src.V2D(), 0); in VisitVecExtractScalar()
Dintrinsics_arm64.cc58 using helpers::OutputRegister;
1195 Register out = OutputRegister(invoke); in VisitStringCompareTo()
2949 Register out = OutputRegister(invoke); in VisitCRC32Update()