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Searched refs:r6 (Results 1 – 9 of 9) sorted by relevance

/art/runtime/arch/mips/
Dinstruction_set_features_mips.cc49 static void GetFlagsFromCppDefined(bool* mips_isa_gte2, bool* r6, bool* fpu_32bit, bool* msa) { in GetFlagsFromCppDefined() argument
66 *r6 = true; in GetFlagsFromCppDefined()
68 *r6 = false; in GetFlagsFromCppDefined()
79 bool r6; in FromVariant() local
81 GetFlagsFromCppDefined(&mips_isa_gte2, &r6, &fpu_32bit, &msa); in FromVariant()
89 r6 = (variant[kPrefixLength] >= '6'); in FromVariant()
106 return MipsFeaturesUniquePtr(new MipsInstructionSetFeatures(fpu_32bit, mips_isa_gte2, r6, msa)); in FromVariant()
112 bool r6 = (bitmap & kR6) != 0; in FromBitmap() local
114 return MipsFeaturesUniquePtr(new MipsInstructionSetFeatures(fpu_32bit, mips_isa_gte2, r6, msa)); in FromBitmap()
120 bool r6; in FromCppDefines() local
[all …]
Dinstruction_set_features_mips.h93 MipsInstructionSetFeatures(bool fpu_32bit, bool mips_isa_gte2, bool r6, bool msa) in MipsInstructionSetFeatures() argument
97 r6_(r6), in MipsInstructionSetFeatures()
100 if (r6) { in MipsInstructionSetFeatures()
/art/compiler/optimizing/
Doptimizing_cfi_test_expected.inc11 // 0x00000000: push {r5, r6, lr}
14 // 0x00000002: .cfi_offset: r6 at cfa-8
29 // 0x0000000e: pop {r5, r6, pc}
79 // 0x00000001: .cfi_offset: r6 at cfa-8
93 // 0x0000000b: .cfi_restore: r6
112 // 0x00000001: .cfi_offset: r6 at cfa-16
134 // 0x00000028: .cfi_restore: r6
241 // 0x00000000: push {r5, r6, lr}
244 // 0x00000002: .cfi_offset: r6 at cfa-8
326 // 0x00000094: pop {r5, r6, pc}
Dcode_generator_arm_vixl.h85 vixl::aarch32::r6,
/art/compiler/jni/
Djni_cfi_test_expected.inc20 // 0x00000000: push {r5,r6,r7,r8,r10,r11,lr}
23 // 0x00000004: .cfi_offset: r6 at cfa-24
79 // 0x00000020: pop {r5,r6,r7,r8,r10,r11,lr}
206 // 0x00000002: .cfi_offset: r6 at cfa-12
230 // 0x00000024: .cfi_restore: r6
275 // 0x00000009: .cfi_offset: r6 at cfa-48
314 // 0x00000076: .cfi_restore: r6
370 // 0x00000030: sw r6, +76(r29)
/art/runtime/arch/arm/
Dquick_entrypoints_arm.S35 .cfi_rel_offset r6, 8
77 .cfi_rel_offset r6, 4
105 .cfi_restore r6
128 .cfi_rel_offset r6, 16
172 .cfi_restore r6
217 .cfi_rel_offset r6, 24
240 .cfi_restore r6
648 pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
659 bx r6
2239 CONDITIONAL_CBZ \reg, r6, \dest
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/art/compiler/utils/arm/
Dassembler_arm_vixl.cc264 tmp_reg = (base.GetCode() != 5) ? r5 : r6; in StoreToOffset()
294 CHECK(tmp_reg.Is(r5) || tmp_reg.Is(r6)) << tmp_reg; in StoreToOffset()
/art/runtime/interpreter/mterp/arm/
Dmain.S100 #define rSELF r6
390 .cfi_rel_offset r6, 12
/art/compiler/utils/
Dassembler_thumb_test_expected.cc.inc2 " 0: e92d 4de0 stmdb sp!, {r5, r6, r7, r8, sl, fp, lr}\n",
152 " 218: e8bd 4de0 ldmia.w sp!, {r5, r6, r7, r8, sl, fp, lr}\n",