Searched refs:w3 (Results 1 – 11 of 11) sorted by relevance
16 FETCH_B w3, 1, 1 // w3<- CC18 GET_VREG w1, w3 // w1<- vCC (requested index)20 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length22 cmp w1, w3 // compare unsigned index, length47 FETCH_B w3, 1, 1 // w3<- CC50 GET_VREG w1, w3 // w1<- vCC (requested index)73 lsr w3, w0, #8 // w3<- CC75 GET_VREG w1, w3 // w1<- vCC (requested index)77 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length79 cmp w1, w3 // compare unsigned index, length[all …]
27 lsr w3, wINST, #8 // w3<- AA33 SET_VREG w0, w3 // vAA<- w039 lsr w3, wINST, #8 // w3<- AA41 SET_VREG w0, w3 // vAA<- w060 lsr w3, wINST, #8 // r3<- AA63 SET_VREG w0, w3 // vAA<- r097 FETCH w3, 4 // w3<- HHHH (high)110 lsr w3, wINST, #8 // w3<- AA113 SET_VREG_WIDE x0, w3119 lsr w3, wINST, #8 // w3<- AA[all …]
47 lsr w3, wINST, #12 // w3<- B49 GET_VREG s1, w381 lsr w3, w0, #8 // w3<- CC84 GET_VREG_DOUBLE $r2, w387 GET_VREG $r2, w3106 lsr w3, wINST, #12 // w3<- B108 GET_VREG $srcreg, w3123 lsr w3, wINST, #12 // w3<- B126 GET_VREG_DOUBLE $srcreg, w3128 GET_VREG_WIDE $srcreg, w3[all …]
20 lsr w3, w0, #8 // w3<- CC22 GET_VREG w1, w3 // w1<- vCC51 lsr w3, wINST, #12 // w3<- B53 GET_VREG w1, w3 // w1<- vB114 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC)116 and w2, w3, #255 // w2<- BB199 lsr w3, wINST, #8 // w3<- AA207 SET_VREG_WIDE x0, w3 // vAA<- x0237 lsr w3, wINST, #12 // w3<- B238 GET_VREG w0, w3 // w0<- vB[all …]
115 cbnz w3, MterpPossibleException // bail out126 GET_VREG w3, w2 // w3<- object we're operating on128 cbz w3, common_errNullObject // object was null149 GET_VREG w3, w2 // w3<- object we're operating on151 cbz w3, common_errNullObject // object was null222 GET_VREG w3, w2 // w3<- fp[B], the object pointer224 cbz w3, common_errNullObject // object was null243 FETCH w3, 1 // w3<- field byte offset
11 GET_VREG w3, w1 // w3<- vB14 cmp w2, w3 // compare (vA, vB)132 lsr w3, wINST, #8 // w3<- AA134 GET_VREG w1, w3 // w1<- vAA
814 LOADREG x8 4 w3 .LfillRegisters938 LOADREG x8 4 w3 .LfillRegisters21159 eor w3, w2, w1 // Prepare the value to store if unlocked1166 stxr w2, w3, [x4]1171 tst w3, #(LOCK_WORD_STATE_MASK_SHIFTED | LOCK_WORD_THIN_LOCK_OWNER_MASK_SHIFTED)1173 add w3, w2, #LOCK_WORD_THIN_LOCK_COUNT_ONE // Increment the recursive lock count.1174 tst w3, #LOCK_WORD_THIN_LOCK_COUNT_MASK_SHIFTED // Test the new thin lock count.1176 stxr w2, w3, [x4]1209 eor w3, w2, w1 // Prepare the value to store if simply locked1213 tst w3, #LOCK_WORD_GC_STATE_MASK_SHIFTED_TOGGLED // Test the non-gc bits.[all …]
35 #define data1w w3
33 int w3; field in Base41 return String.format("w0: %d, w1: %d, w2: %d, w3: %d", w0, w1, w2, w3); in baseString()
146 // 0x0000003c: str w3, [sp, #212]
639 EXPECT_TRUE(vixl::aarch64::w3.Is(Arm64Assembler::reg_w(W3))); in TEST()