Searched refs:BIT_1 (Results 1 – 2 of 2) sorted by relevance
196 #define BIT_1 (1 << 1) macro342 #define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */375 #define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */392 #define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */405 #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */803 #define CS_RST_CLR BIT_1 /* Clear Software Reset */807 #define LED_STAT_ON BIT_1 /* Status LED On */817 #define PC_VCC_ON BIT_1 /* Switch VCC On */847 #define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */878 #define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */[all …]
202 #define BIT_1 0x0002 macro297 #define MDI_SR_JABBER_DETECT BIT_1 // Jabber detected329 #define NWAY_EX_PAGE_RECEIVED BIT_1 // link code word received338 #define PHY_100_ER0_SPEED_INDIC BIT_1 // 1 = 100mbs, 0= 10mbs505 #define CFIG_URUN_RETRY BIT_1 OR BIT_2533 #define CFIG_BROADCAST_DISABLE BIT_1542 #define CFIG_PADDING BIT_1