Home
last modified time | relevance | path

Searched refs:IO_BASE_ADDRESS (Results 1 – 11 of 11) sorted by relevance

/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/
DPlatformEarlyInit.c347 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
348 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
349 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
350 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
351 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
352 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
353 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
354 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
355 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
356 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
[all …]
DPchInitPeim.c468 MmioOr32 (IO_BASE_ADDRESS + 0x0520, 0x01); // UART3_RXD-L
469 MmioOr32 (IO_BASE_ADDRESS + 0x0530, 0x01); // UART3_TXD-0
476 MmioAnd32 (IO_BASE_ADDRESS + 0x0520, ~(UINT32)0x07);
477 MmioAnd32 (IO_BASE_ADDRESS + 0x0530, ~(UINT32)0x07);
486 MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);
487 MmioOr8 (IO_BASE_ADDRESS + 0x0090, 0x01);
488 MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);
489 MmioOr8 (IO_BASE_ADDRESS + 0x00D0, 0x01);
503 MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07); in IchRcrbInit()
504 MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);
[all …]
DBootMode.c185 …GpioValue = MmioRead32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + PMU_PWRBTN_B_OFFSET); // The value…
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/
DUartInit.c40 #define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address macro
188 MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187)); in EnableInternalUart()
189 MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L in EnableInternalUart()
190 MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007)); in EnableInternalUart()
191 MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L in EnableInternalUart()
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/MonoStatusCode/
DPlatformStatusCode.c356 MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187)); in EnableInternalUart()
357 MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L in EnableInternalUart()
358 MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007)); in EnableInternalUart()
359 MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L in EnableInternalUart()
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/
DPlatformBaseAddresses.h62 #define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address macro
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/
DBoardGpios.c251 …mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].off… in InternalGpioConfig()
252 …mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].off… in InternalGpioConfig()
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/
DPlatform.c309 …mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].off… in TristateLpcGpioConfig()
310 …mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].off… in TristateLpcGpioConfig()
613 mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset; in TristateLpcGpioS0i3Config()
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/
DI2CLibPei.c118 I2CLibPeiMmioWrite32(IO_BASE_ADDRESS+I2CGPIO[Index], 0x2003CC81); in IntelI2CPeiLibConstructor()
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformPei/
DPlatform.c597 (UINT32)((IO_BASE_ADDRESS & B_PCH_LPC_IO_BASE_BAR) | B_PCH_LPC_IO_BASE_EN)
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/PlatformBdsLib/
DBdsPlatform.c2571 GpioValue = MmioRead32 (IO_BASE_ADDRESS + 0x0668); // The value of GPIOC_5 in ShowProgressHotKey()