Searched refs:MPIDR_AFFLVL0 (Results 1 – 16 of 16) sorted by relevance
76 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in poplar_pwr_domain_on_finish()120 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in poplar_validate_power_state()122 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state()147 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in poplar_get_sys_suspend_power_state()
23 ((state)->pwr_domain_state[MPIDR_AFFLVL0])166 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in hikey_get_sys_suspend_power_state()231 if (pwr_lvl != MPIDR_AFFLVL0) in hikey_validate_power_state()234 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey_validate_power_state()237 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in hikey_validate_power_state()
45 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; in tegra_soc_validate_power_state()55 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; in tegra_soc_validate_power_state()63 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in tegra_soc_validate_power_state()119 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; in tegra_soc_pwr_domain_suspend()
23 ((state)->pwr_domain_state[MPIDR_AFFLVL0])142 if (pwr_lvl != MPIDR_AFFLVL0) in hikey960_validate_power_state()145 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey960_validate_power_state()148 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in hikey960_validate_power_state()279 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in hikey960_get_sys_suspend_power_state()
220 if (target_afflvl == MPIDR_AFFLVL0) { in plat_affinst_standby()248 if (afflvl != MPIDR_AFFLVL0) in plat_affinst_on()291 if (afflvl != MPIDR_AFFLVL0) { in plat_affinst_off()334 if (afflvl >= MPIDR_AFFLVL0) in plat_affinst_suspend()410 if (afflvl >= MPIDR_AFFLVL0) in plat_affinst_suspend_finish()
49 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),52 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),171 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in qemu_pwr_domain_on_finish()
19 ((state)->pwr_domain_state[MPIDR_AFFLVL0])147 if (pwr_lvl != MPIDR_AFFLVL0) in rockchip_validate_power_state()150 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in rockchip_validate_power_state()153 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in rockchip_validate_power_state()173 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rockchip_get_sys_suspend_power_state()
280 if (target_afflvl == MPIDR_AFFLVL0) { in plat_affinst_standby()322 if (afflvl != MPIDR_AFFLVL0) in plat_affinst_on()396 if (afflvl != MPIDR_AFFLVL0) { in plat_affinst_off()463 if (afflvl >= MPIDR_AFFLVL0) in plat_affinst_suspend()557 assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF); in plat_power_domain_on_finish()606 if (afflvl >= MPIDR_AFFLVL0) in plat_affinst_suspend_finish()658 for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in plat_get_sys_suspend_power_state()
72 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; in tegra_soc_validate_power_state()97 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & in tegra_soc_pwr_domain_suspend()279 int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; in tegra_soc_pwr_domain_on_finish()
52 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in tegra_soc_validate_power_state()
302 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state()304 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state()
149 afflvl >= (int) MPIDR_AFFLVL0; afflvl--) { in plat_get_power_domain_tree_desc()
116 for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in tegra_get_sys_suspend_power_state()
34 #define ARM_PWR_LVL0 MPIDR_AFFLVL0
37 #define MPIDR_AFFLVL0 0 macro
40 #define MPIDR_AFFLVL0 U(0) macro