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Searched refs:RB_ADDR (Results 1 – 2 of 2) sorted by relevance

/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/
Dif_msk.c2572 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txsq, RB_CTRL), RB_RST_SET); in msk_init()
2674 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); in msk_set_rambuffer()
2675 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_START), sc->msk_rxqstart[port] / 8); in msk_set_rambuffer()
2676 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_END), sc->msk_rxqend[port] / 8); in msk_set_rambuffer()
2677 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_WP), sc->msk_rxqstart[port] / 8); in msk_set_rambuffer()
2678 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_RP), sc->msk_rxqstart[port] / 8); in msk_set_rambuffer()
2685 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_RX_UTPP), utpp); in msk_set_rambuffer()
2686 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_RX_LTPP), ltpp); in msk_set_rambuffer()
2689 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); in msk_set_rambuffer()
2690 CSR_READ_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL)); in msk_set_rambuffer()
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Dif_mskreg.h1204 #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) macro