Searched refs:SPD_SDRAM_TCLK1_PULSE (Results 1 – 2 of 2) sorted by relevance
43 #define SPD_SDRAM_TCLK1_PULSE 9 // cycle time for highest cas latency macro
39 #define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency macro