Searched refs:SPD_SDRAM_TCLK3_PULSE (Results 1 – 2 of 2) sorted by relevance
47 #define SPD_SDRAM_TCLK3_PULSE 25 // cycle time for 3rd highest cas latency macro
43 #define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency macro