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/device/linaro/hikey/installer/hikey/
Dhisi-idt.py84 self.chip = chiptype
118 data = array.array('B', self.startframe[self.chip]).tostring()
126 self.headframe[self.chip][4] = (length>>24)&0xff
127 self.headframe[self.chip][5] = (length>>16)&0xff
128 self.headframe[self.chip][6] = (length>>8)&0xff
129 self.headframe[self.chip][7] = (length)&0xff
130 self.headframe[self.chip][8] = (address>>24)&0xff
131 self.headframe[self.chip][9] = (address>>16)&0xff
132 self.headframe[self.chip][10] = (address>>8)&0xff
133 self.headframe[self.chip][11] = (address)&0xff
[all …]
/device/linaro/bootloader/OpenPlatformPkg/Documentation/Marvell/PortingGuide/
DComPhy.txt10 Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
13 Every chip has 8 ComPhy PCDs and three of them concern lanes settings for this
14 chip. Below is example for the first chip (Chip0).
20 Unicode string indicating type of chip - currently supported is
43 Below is example for the first chip (Chip0).
DMpp.txt15 <Num> stands for chip ID (order is not important, but configuration will be
18 Below is example for the first chip (Chip0).
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
DPL35xSmc.h30 #define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23)) argument
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/
DSASSSDT.ASL60 376, //chip fatal error irq(120)
61 381, //chip fatal error irq(125)
128 376, //chip fatal error irq(120)
129 381, //chip fatal error irq(125)
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciSioSerialDxe/
DPciSioSerialDxe.uni2 // Serial driver for standard UARTS on a SIO chip or PCI/PCIE card.
19 …RACT #language en-US "Serial driver for standard UARTS on a SIO chip or PCI/PCIE card."
DPciSioSerialDxe.inf2 # Serial driver for standard UARTS on a SIO chip or PCI/PCIE card.
/device/linaro/bootloader/arm-trusted-firmware/docs/plat/
Dsocionext-uniphier.rst9 non-volatile storage to the on-chip SRAM. Unfortunately, BL1 does not fit in
12 in the on-chip SRAM, initializes the DRAM, expands BL1 there, and hands the
24 (and verified if the chip fuses are blown).
36 compressed-BL1 appended) into the on-chip SRAM. If the SoC fuses are blown,
41 This runs in the on-chip SRAM. After the minimum SoC initialization and DRAM
/device/linaro/hikey/wpan/
DREADME5 bt_sco_app - Command line application to send PCM configuruations to WL12xx chip(optional)
/device/linaro/bootloader/OpenPlatformPkg/Documentation/Marvell/Drivers/
DSpiDriver.txt41 //Allocate and zero all fields in the SPI_DEVICE struct. Set the chip
45 param[IN] Cs Chip select ID of the slave chip.
/device/linaro/bootloader/OpenPlatformPkg/Applications/EepromCmd/
DEepromCmd.uni63 "Read 16 bytes from address 0x0 in chip 0x57:\r\n"
65 "Fill 16 bytes with 0xab at address 0x0 in chip 0x57:\r\n"
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/
DD05Pci.asl22 /* 0xD000E014:Hi1616 chip version reg[19:8], 0x102-after EC, 0x101/0-before EC. */
29 /* RBYV:Return by chip version
30 * the pcie device should be disable for chip's reason before EC,
/device/linaro/bootloader/edk2/OvmfPkg/
DOvmfPkg.dec146 # used by OVMF, the varstore pflash chip, LockBox etc).
/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/DeviceTree/
Dhi3660-hikey960.dts203 * NC = not connected (pin out but not routed from the chip to
/device/linaro/bootloader/arm-trusted-firmware/docs/
Dchange-log.rst664 - While this version has low on-chip RAM requirements, there are further
828 - While this version greatly reduces the on-chip RAM requirements, there are
982 - While this version greatly reduces the on-chip RAM requirements, there are
1128 - The ARM Trusted Firmware still uses too much on-chip Trusted SRAM. A number
1272 - The ARM Trusted Firmware uses too much on-chip Trusted SRAM. Currently the
/device/linaro/bootloader/edk2/SecurityPkg/
DSecurityPkg.uni83 …mClass_HELP #language en-US "Specifies the type of TCG platform that contains TPM chip.<BR><BR>\n"
DSecurityPkg.dec289 ## Specifies the type of TCG platform that contains TPM chip.<BR><BR>