Searched refs:mr (Results 1 – 5 of 5) sorted by relevance
249 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; in ddr3_get_parameter()252 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; in ddr3_get_parameter()255 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; in ddr3_get_parameter()259 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; in ddr3_get_parameter()263 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; in ddr3_get_parameter()265 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); in ddr3_get_parameter()266 pdram_timing->mr[3] = 0; in ddr3_get_parameter()286 pdram_timing->mr[0] = DDR3_BC4 in ddr3_get_parameter()290 pdram_timing->mr[0] = DDR3_BL8 in ddr3_get_parameter()436 pdram_timing->mr[2] = LPDDR2_RL4_WL2; in lpddr2_get_parameter()[all …]
594 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | in gen_rk3399_ctl_params_f0()595 pdram_timing->mr[0]); in gen_rk3399_ctl_params_f0()597 pdram_timing->mr[2]); in gen_rk3399_ctl_params_f0()599 pdram_timing->mr[3]); in gen_rk3399_ctl_params_f0()603 (pdram_timing->mr[1] << 16) | in gen_rk3399_ctl_params_f0()604 pdram_timing->mr[0]); in gen_rk3399_ctl_params_f0()606 pdram_timing->mr[2]); in gen_rk3399_ctl_params_f0()608 pdram_timing->mr[3]); in gen_rk3399_ctl_params_f0()845 pdram_timing->mr[0] << 16); in gen_rk3399_ctl_params_f1()846 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | in gen_rk3399_ctl_params_f1()[all …]
131 uint32_t mr[4]; member
720 mr = MyRef(o, value=24)721 self.assertTrue(mr() is o)722 self.assertTrue(mr.called)723 self.assertEqual(mr.value, 24)725 self.assertTrue(mr() is None)726 self.assertTrue(mr.called)
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