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/external/elfutils/libcpu/
Dbpf_disasm.c65 #define A32(O, S) REG(1) " = " REGU(1) " " #O " " S macro
174 code_fmt = A32(+, IMMS(2)); in bpf_disasm()
177 code_fmt = A32(-, IMMS(2)); in bpf_disasm()
180 code_fmt = A32(*, IMMS(2)); in bpf_disasm()
183 code_fmt = A32(/, IMMS(2)); in bpf_disasm()
186 code_fmt = A32(|, IMMX(2)); in bpf_disasm()
189 code_fmt = A32(&, IMMX(2)); in bpf_disasm()
192 code_fmt = A32(<<, IMMS(2)); in bpf_disasm()
195 code_fmt = A32(>>, IMMS(2)); in bpf_disasm()
198 code_fmt = A32(%%, IMMS(2)); in bpf_disasm()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dstack-alignment.ll2 ; RUN: llc -march=mipsel -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-32
7 ; RUN: llc -march=mips64el -mcpu=mips64 -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-64
11 ; A32-32: addiu $sp, $sp, -32
12 ; A32-64: daddiu $sp, $sp, -32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfp16-instructions.ll7 …i -mattr=+vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16,CHECK-SOFTFP-FP16-A32
715 ; CHECK-SOFTFP-FP16-A32: vcmp.f32 s0, s0
716 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
717 ; CHECK-SOFTFP-FP16-A32-NEXT: vmoveq.f32 s{{.}}, s{{.}}
741 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
742 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
743 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovge.f32 s{{.}}, s{{.}}
762 ; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
763 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
764 ; CHECK-SOFTFP-FP16-A32-NEXT: vmovls.f32 s{{.}}, s{{.}}
[all …]
Dbuild-attributes.ll120 …UN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a32 | FileCheck %s --check-prefix=CORTEX-A32
121 …nfs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A32-FAST
1321 ; CORTEX-A32: .cpu cortex-a32
1322 ; CORTEX-A32: .eabi_attribute 6, 14
1323 ; CORTEX-A32: .eabi_attribute 7, 65
1324 ; CORTEX-A32: .eabi_attribute 8, 1
1325 ; CORTEX-A32: .eabi_attribute 9, 2
1326 ; CORTEX-A32: .fpu crypto-neon-fp-armv8
1327 ; CORTEX-A32: .eabi_attribute 12, 3
1328 ; CORTEX-A32-NOT: .eabi_attribute 27
[all …]
/external/llvm/test/CodeGen/ARM/
Dbuild-attributes.ll111 …UN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a32 | FileCheck %s --check-prefix=CORTEX-A32
112 …nfs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A32-FAST
1254 ; CORTEX-A32: .cpu cortex-a32
1255 ; CORTEX-A32: .eabi_attribute 6, 14
1256 ; CORTEX-A32: .eabi_attribute 7, 65
1257 ; CORTEX-A32: .eabi_attribute 8, 1
1258 ; CORTEX-A32: .eabi_attribute 9, 2
1259 ; CORTEX-A32: .fpu crypto-neon-fp-armv8
1260 ; CORTEX-A32: .eabi_attribute 12, 3
1261 ; CORTEX-A32-NOT: .eabi_attribute 19
[all …]
/external/vixl/examples/aarch32/
Dabs.cc45 MacroAssembler masm(A32); in main()
/external/vixl/benchmarks/aarch32/
Dbench-dataop.cc86 benchmark(instructions, A32); in main()
Dbench-branch-masm.cc91 benchmark(iterations, A32); in main()
Dbench-literal.cc98 benchmark(iterations, literals, A32); in main()
Dbench-branch-link-masm.cc101 benchmark(iterations, A32); in main()
/external/vixl/src/aarch32/
Dconstants-aarch32.h41 enum InstructionSet { A32, T32 }; enumerator
45 const InstructionSet kDefaultISA = A32;
Dlocation-aarch32.h82 VIXL_ASSERT(isa == A32); in EmitOperator()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Df16-instructions.ll29 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]
31 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
44 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]
46 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
88 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]
90 ; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
103 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]
105 ; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%f[0-9]+]], [[Z]], [[A32]];
118 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]
120 ; CHECK-NOF16-NEXT: mul.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
[all …]
Dparam-load-store.ll51 ; CHECK: cvt.u32.u16 [[A32:%r[0-9]+]], [[A8]];
52 ; CHECK: and.b32 [[A1:%r[0-9]+]], [[A32]], 1;
133 ; CHECK: cvt.u32.u16 [[A32:%r[0-9]+]], [[A8]];
134 ; CHECK: and.b32 [[A:%r[0-9]+]], [[A32]], 255;
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-arm-instructions-v8.s1 @ New ARMv8 A32 encodings
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions-v8.s1 @ New ARMv8 A32 encodings
/external/vixl/doc/aarch32/
Dgetting-started-aarch32.md223 If you generated T32 code instead of A32 code, you must use
225 mixed T32 and A32 code, the result won't be accurate (everything will be
226 disassembled as T32 or A32 code).
/external/vixl/test/aarch32/
Dtest-assembler-aarch32.cc62 void Test##Name() { Test##Name##Impl(A32); } \
77 Test##Name##Impl(A32); \
3106 VIXL_CHECK(assm.GetInstructionSetInUse() == A32); in CheckInstructionSetA32()
3143 CheckInstructionSetA32(Assembler(A32)); in TEST_NOASM()
3144 CheckInstructionSetA32(Assembler(1024, A32)); in TEST_NOASM()
3145 CheckInstructionSetA32(Assembler(buffer, sizeof(buffer), A32)); in TEST_NOASM()
3147 CheckInstructionSetA32(MacroAssembler(A32)); in TEST_NOASM()
3148 CheckInstructionSetA32(MacroAssembler(1024, A32)); in TEST_NOASM()
3149 CheckInstructionSetA32(MacroAssembler(buffer, sizeof(buffer), A32)); in TEST_NOASM()
3178 assm.UseInstructionSet(A32); in TEST_NOASM()
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/external/vixl/test/aarch32/config/
Dtemplate-assembler-negative-aarch32.cc.in101 masm.IsUsingT32() ? "T32" : "A32");
/external/capstone/bindings/ocaml/
Dcapstone.ml34 | CS_MODE_V8 (* ARMv8 A32 encodings for ARM *)
/external/llvm/docs/
DBigEndianNEON.rst15 …ghout, but is almost applicable to the A32/ARMv7 instruction sets also. The ABI format for passing…
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DBigEndianNEON.rst15 …ghout, but is almost applicable to the A32/ARMv7 instruction sets also. The ABI format for passing…
/external/vixl/
DREADME.md18 1. Programmatic **assemblers** to generate A64, A32 or T32 code at runtime. The
/external/icu/icu4c/source/data/unidata/
DDerivedCoreProperties.txt390 0A32..0A33 ; Alphabetic
1136 11A0B..11A32 ; Alphabetic
5909 0A32..0A33 ; ID_Start
6381 11A0B..11A32 ; ID_Start
6655 0A32..0A33 ; ID_Continue
7545 11A0B..11A32 ; ID_Continue
7824 0A32..0A33 ; XID_Start
8300 11A0B..11A32 ; XID_Start
8570 0A32..0A33 ; XID_Continue
9465 11A0B..11A32 ; XID_Continue
[all …]
/external/capstone/
DChangeLog356 - Support new mode CS_MODE_V8 for Armv8 A32 encodings.

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