| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | vecreduce-propagate-sd-flags.ll | 8 ; CHECK: Legalizing node: [[VFOUR:t.*]]: v4f64 = BUILD_VECTOR
10 ; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR
12 ; CHECK: Legalizing node: [[VTWO:t.*]]: v2f64 = BUILD_VECTOR
13 ; CHECK: Legally typed node: [[VTWO]]: v2f64 = BUILD_VECTOR
|
| D | arm64-build-vector.ll | 30 ; fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
31 ; -> (BUILD_VECTOR A, B, ..., C, D, ...)
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-build-vector.ll | 48 ; fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
49 ; -> (BUILD_VECTOR A, B, ..., C, D, ...)
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 429 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in SPUTargetLowering()
1098 SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T); in LowerConstantFP()
1677 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T)); in LowerBUILD_VECTOR()
1687 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T)); in LowerBUILD_VECTOR()
1697 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size())); in LowerBUILD_VECTOR()
1705 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); in LowerBUILD_VECTOR()
1709 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T); in LowerBUILD_VECTOR()
1731 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in LowerV2I64Splat()
1747 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, in LowerV2I64Splat()
1760 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in LowerV2I64Splat()
[all …]
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| D | SPUISelDAGToDAG.cpp | 124 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in getCarryGenerateShufMask()
139 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in getBorrowGenerateShufMask()
665 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in Select()
673 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in Select()
681 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in Select()
823 signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl, in Select()
837 SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, in Select()
1188 } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) { in SelectI64Constant()
|
| D | SPUOperands.td | 34 assert(N->getOpcode() == ISD::BUILD_VECTOR
35 && "LO16_vec got something other than a BUILD_VECTOR");
60 assert(N->getOpcode() == ISD::BUILD_VECTOR
61 && "HI16_vec got something other than a BUILD_VECTOR");
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | DAGCombiner_illegal_BUILD_VECTOR.ll | 4 ; BUILD_VECTOR node.
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 52 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; in ScalarizeVectorResult()
357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), in ScalarizeVecOp_CONCAT_VECTORS()
424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; in SplitVectorResult()
577 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); in SplitVecRes_BUILD_VECTOR()
580 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); in SplitVecRes_BUILD_VECTOR()
930 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); in SplitVecRes_VECTOR_SHUFFLE()
1165 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), in SplitVecOp_CONCAT_VECTORS()
1233 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; in WidenVectorResult()
1533 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); in WidenVecRes_Convert()
1657 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, in WidenVecRes_BITCAST()
[all …]
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| D | LegalizeTypesGeneric.cpp | 289 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Parts, 2); in ExpandOp_BITCAST()
323 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, in ExpandOp_BUILD_VECTOR()
384 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); in ExpandOp_SCALAR_TO_VECTOR()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | vbinop-simplify-bug.ll | 12 ; Cannot select: 0x2e329d0: v4i32 = BUILD_VECTOR 0x2e2ea00, 0x2e2ea00, 0x2e2ea00, 0x2e2ea00
|
| D | 2011-12-28-vselecti8.ll | 7 ; wider BUILD_VECTOR. This causes the introduction of a new
|
| /external/llvm/test/CodeGen/X86/ |
| D | vbinop-simplify-bug.ll | 12 ; Cannot select: 0x2e329d0: v4i32 = BUILD_VECTOR 0x2e2ea00, 0x2e2ea00, 0x2e2ea00, 0x2e2ea00
|
| D | 2011-12-28-vselecti8.ll | 7 ; wider BUILD_VECTOR. This causes the introduction of a new
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
497 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op); in ScalarizeVecOp_UnaryOp()
505 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops); in ScalarizeVecOp_CONCAT_VECTORS()
595 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; in SplitVectorResult()
802 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps); in SplitVecRes_BUILD_VECTOR()
805 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps); in SplitVecRes_BUILD_VECTOR()
1412 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps); in SplitVecRes_VECTOR_SHUFFLE()
1655 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps); in SplitVecOp_EXTRACT_VECTOR_ELT()
1923 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts); in SplitVecOp_CONCAT_VECTORS()
2059 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; in WidenVectorResult()
[all …]
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| D | LegalizeTypesGeneric.cpp | 371 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, in ExpandOp_BITCAST()
405 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, in ExpandOp_BUILD_VECTOR()
467 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in ExpandOp_SCALAR_TO_VECTOR()
|
| D | LegalizeVectorOps.cpp | 623 Value = DAG.getNode(ISD::BUILD_VECTOR, dl, in ExpandLoad()
733 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand) in ExpandSELECT()
749 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops); in ExpandSELECT()
1066 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in UnrollVSETCC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | vector-DAGCombine.ll | 72 ; Test folding a binary vector operation with constant BUILD_VECTOR
136 ; a BUILD_VECTOR with i32 0 operands, which did not match the i16 operands
137 ; of the other BUILD_VECTOR.
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vector-DAGCombine.ll | 72 ; Test folding a binary vector operation with constant BUILD_VECTOR
136 ; a BUILD_VECTOR with i32 0 operands, which did not match the i16 operands
137 ; of the other BUILD_VECTOR.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/ |
| D | isel-build-undef.ll | 3 ; During lowering, a BUILD_VECTOR of undef values was created. This was
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 253 BUILD_VECTOR, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 269 BUILD_VECTOR, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 303 BUILD_VECTOR, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1688 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in CompactSwizzlableVector()
1730 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in ReorganizeVector()
1769 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR); in OptimizeSwizzle()
1900 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
1912 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1942 if (Arg.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1949 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in PerformDAGCombine()
2010 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
2028 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenDAGISel.inc | 11590 /* 21388*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11598 /* 21403*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11691 /* 21578*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11789 /* 21760*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11797 /* 21775*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11891 /* 21951*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11990 /* 22134*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11998 /* 22148*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12051 /* 22242*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12108 /* 22343*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
[all …]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1840 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in CompactSwizzlableVector()
1882 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in ReorganizeVector()
1921 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR); in OptimizeSwizzle()
2009 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
2021 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
2051 if (Arg.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
2058 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
2117 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
2136 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
|