Searched refs:CACHELINE_SIZE (Results 1 – 6 of 6) sorted by relevance
18 #define CACHELINE_SIZE 128 macro38 for (unsigned long j = 0; j < zero_size; j += CACHELINE_SIZE) in syscall_loop()67 p = (char *)memalign(zero_size, CACHELINE_SIZE); in rfi_flush_test()79 l1d_misses_expected = iterations * (zero_size / CACHELINE_SIZE - 2); in rfi_flush_test()
22 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro52 flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); in dwc3_flush_cache()
27 #define CACHELINE_SIZE 64 macro44 p += CACHELINE_SIZE; in gen_clflush_range()
403 #define CACHELINE_SIZE 64 macro405 #define CACHELINE_SIZE 128 macro409 #define CACHELINE_SIZE 64 macro416 #define CACHELINE_SIZE 32 macro418 #define CACHELINE_SIZE 64 macro422 #ifndef CACHELINE_SIZE // NOLINT425 #define CACHELINE_SIZE 64 macro428 #define CACHELINE_ALIGNED __attribute__((aligned(CACHELINE_SIZE)))729 #define CACHELINE_SIZE 64 macro
26 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro38 flush_dcache_range(addr & ~(CACHELINE_SIZE - 1), in xhci_flush_cache()39 ALIGN(addr + len, CACHELINE_SIZE)); in xhci_flush_cache()53 invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1), in xhci_inval_cache()54 ALIGN(addr + len, CACHELINE_SIZE)); in xhci_inval_cache()192 size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE); in xhci_malloc()
915 p += CACHELINE_SIZE; in anv_cmd_buffer_add_secondary()1364 for (uint32_t i = 0; i < (*bbo)->length; i += CACHELINE_SIZE) in setup_execbuf_for_cmd_buffer()