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Searched refs:CACHELINE_SIZE (Results 1 – 6 of 6) sorted by relevance

/external/linux-kselftest/tools/testing/selftests/powerpc/security/
Drfi_flush.c18 #define CACHELINE_SIZE 128 macro
38 for (unsigned long j = 0; j < zero_size; j += CACHELINE_SIZE) in syscall_loop()
67 p = (char *)memalign(zero_size, CACHELINE_SIZE); in rfi_flush_test()
79 l1d_misses_expected = iterations * (zero_size / CACHELINE_SIZE - 2); in rfi_flush_test()
/external/u-boot/drivers/usb/dwc3/
Dio.h22 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
52 flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); in dwc3_flush_cache()
/external/mesa3d/src/intel/common/
Dgen_clflush.h27 #define CACHELINE_SIZE 64 macro
44 p += CACHELINE_SIZE; in gen_clflush_range()
/external/dynamic_depth/internal/base/
Dport.h403 #define CACHELINE_SIZE 64 macro
405 #define CACHELINE_SIZE 128 macro
409 #define CACHELINE_SIZE 64 macro
416 #define CACHELINE_SIZE 32 macro
418 #define CACHELINE_SIZE 64 macro
422 #ifndef CACHELINE_SIZE // NOLINT
425 #define CACHELINE_SIZE 64 macro
428 #define CACHELINE_ALIGNED __attribute__((aligned(CACHELINE_SIZE)))
729 #define CACHELINE_SIZE 64 macro
/external/u-boot/drivers/usb/host/
Dxhci-mem.c26 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
38 flush_dcache_range(addr & ~(CACHELINE_SIZE - 1), in xhci_flush_cache()
39 ALIGN(addr + len, CACHELINE_SIZE)); in xhci_flush_cache()
53 invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1), in xhci_inval_cache()
54 ALIGN(addr + len, CACHELINE_SIZE)); in xhci_inval_cache()
192 size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE); in xhci_malloc()
/external/mesa3d/src/intel/vulkan/
Danv_batch_chain.c915 p += CACHELINE_SIZE; in anv_cmd_buffer_add_secondary()
1364 for (uint32_t i = 0; i < (*bbo)->length; i += CACHELINE_SIZE) in setup_execbuf_for_cmd_buffer()