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Searched refs:CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dclock_manager_gen5.h205 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 macro
/external/u-boot/arch/arm/mach-socfpga/
Dclock_manager_gen5.c430 reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> in cm_get_l4_sp_clk_hz()