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Searched refs:COMMON_PHY_CFG1_CORE_RSTN_OFFSET (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/phy/marvell/
Dcomphy.h31 #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14 macro
33 (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
Dcomphy_cp110.c144 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_pcie_power_up()
153 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_pcie_power_up()
539 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_usb3_power_up()
548 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_usb3_power_up()
712 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_sata_power_up()