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Searched refs:CONFIG_SYS_DDR_TIMING_5_800 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/include/configs/
DBSC9132QDS.h144 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 macro
179 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
191 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
/external/u-boot/board/freescale/bsc9132qds/
Dspl_minimal.c39 __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5); in sdram_init()
/external/u-boot/scripts/
Dconfig_whitelist.txt2500 CONFIG_SYS_DDR_TIMING_5_800