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Searched refs:CPLL_MODE_SHIFT (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rk3188.c233 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
380 CPLL_MODE_MASK << CPLL_MODE_SHIFT, in rkclk_init()
382 CPLL_MODE_SLOW << CPLL_MODE_SHIFT); in rkclk_init()
450 CPLL_MODE_MASK << CPLL_MODE_SHIFT, in rkclk_init()
452 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); in rkclk_init()
Dclk_rk3288.c386 CPLL_MODE_SLOW << CPLL_MODE_SHIFT); in rkclk_init()
447 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); in rkclk_init()
500 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
Dclk_rk3128.c228 CPLL_MODE_NORM << CPLL_MODE_SHIFT); in rkclk_init()
246 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
Dclk_rk3328.c74 CPLL_MODE_SHIFT = 8, enumerator
225 mode_shift = CPLL_MODE_SHIFT; in rkclk_set_pll()
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rk322x.h95 CPLL_MODE_SHIFT = 8, enumerator
96 CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
Dcru_rk3128.h97 CPLL_MODE_SHIFT = 8, enumerator
98 CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
Dcru_rk3288.h183 CPLL_MODE_SHIFT = 8, enumerator
184 CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT,
Dcru_rk3188.h157 CPLL_MODE_SHIFT = 8, enumerator