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Searched refs:CRm (Results 1 – 25 of 36) sorted by relevance

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/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
98 Ops[4].getAsInteger(10, CRm); in parseGenericRegister()
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
110 uint32_t CRm = (Bits >> 3) & 0xf; in genericRegisterString() local
114 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp122 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
127 Ops[4].getAsInteger(10, CRm); in parseGenericRegister()
129 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
139 uint32_t CRm = (Bits >> 3) & 0xf; in genericRegisterString() local
143 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td371 // op1 CRn CRm op2
390 // op1 CRn CRm op2
469 // Op0 Op1 CRn CRm Op2
530 // Op0 Op1 CRn CRm Op2
569 // Op0 Op1 CRn CRm Op2
580 // Op0 Op1 CRn CRm Op2
586 // Op0 Op1 CRn CRm Op2
591 // Op0 Op1 CRn CRm Op2
601 // Op0 Op1 CRn CRm Op2
607 // Op0 Op1 CRn CRm Op2
[all …]
DAArch64InstrFormats.td1067 // Hint instructions that take both a CRm and a 3-bit immediate.
1081 // CRm. op2 differentiates the opcodes.
1092 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
1094 bits<4> CRm;
1096 let Inst{11-8} = CRm;
1103 bits<4> CRm;
1104 let CRm = 0b0011;
1106 let Inst{11-8} = CRm;
1118 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
1145 // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
DAArch64InstrInfo.td455 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
458 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
461 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
464 let CRm = 0b0010;
534 let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in {
541 let Uses = [LR], Defs = [LR], CRm = 0b0000 in {
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td311 // Op0 Op1 CRn CRm Op2
366 // Op0 Op1 CRn CRm Op2
405 // Op0 Op1 CRn CRm Op2
416 // Op0 Op1 CRn CRm Op2
421 // Op0 Op1 CRn CRm Op2
431 // Op0 Op1 CRn CRm Op2
437 // Op0 Op1 CRn CRm Op2
442 // Op0 Op1 CRn CRm Op2
454 // Op0 Op1 CRn CRm Op2
709 // Op0 Op1 CRn CRm Op2
[all …]
DAArch64InstrFormats.td856 // Hint instructions that take both a CRm and a 3-bit immediate.
870 // CRm. op2 differentiates the opcodes.
881 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
883 bits<4> CRm;
885 let Inst{11-8} = CRm;
896 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
923 // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
/external/capstone/arch/AArch64/
DAArch64BaseInfo.c633 uint32_t Op0, Op1, CRn, CRm, Op2; in A64SysRegMapper_toString() local
671 CRm = (Bits >> 3) & 0xf; in A64SysRegMapper_toString()
687 CRmS = utostr(CRm, false); in A64SysRegMapper_toString()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td4143 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4153 bits<4> CRm;
4160 let Inst{3-0} = CRm;
4168 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4177 bits<4> CRm;
4183 let Inst{3-0} = CRm;
4192 c_imm:$CRm, imm0_7:$opc2),
4194 imm:$CRm, imm:$opc2)]>,
4196 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4198 c_imm:$CRm, 0, pred:$p)>;
[all …]
DARMInstrInfo.td5079 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5080 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5082 imm:$CRm, imm:$opc2)]>,
5089 bits<4> CRm;
5091 let Inst{3-0} = CRm;
5103 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5104 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5106 imm:$CRm, imm:$opc2)]>,
5114 bits<4> CRm;
5116 let Inst{3-0} = CRm;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td4151 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4161 bits<4> CRm;
4168 let Inst{3-0} = CRm;
4174 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4183 bits<4> CRm;
4189 let Inst{3-0} = CRm;
4196 c_imm:$CRm, imm0_7:$opc2),
4198 imm:$CRm, imm:$opc2)]>,
4200 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4202 c_imm:$CRm, 0, pred:$p)>;
[all …]
DARMInstrInfo.td4813 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4816 imm:$CRm, imm:$opc2)]>,
4823 bits<4> CRm;
4825 let Inst{3-0} = CRm;
4835 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4838 imm:$CRm, imm:$opc2)]>,
4846 bits<4> CRm;
4848 let Inst{3-0} = CRm;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrInfo.td4215 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4216 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4218 imm:$CRm, imm:$opc2)]> {
4224 bits<4> CRm;
4226 let Inst{3-0} = CRm;
4236 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4237 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4239 imm:$CRm, imm:$opc2)]> {
4246 bits<4> CRm;
4248 let Inst{3-0} = CRm;
[all …]
DARMInstrThumb2.td3620 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3630 bits<4> CRm;
3637 let Inst{3-0} = CRm;
3644 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3645 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3654 bits<4> CRm;
3660 let Inst{3-0} = CRm;
3667 c_imm:$CRm, imm0_7:$opc2),
3669 imm:$CRm, imm:$opc2)]>;
3672 c_imm:$CRm, imm0_7:$opc2),
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc20350 …2] }):$CRm) => (MCRR (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, G…
20356 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRm
20390 …2] }):$CRm) => (MCRR2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, …
20396 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRm
20428 …[i32] }):$CRm) => (t2MCRR (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, …
20434 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRm
20468 …[i32] }):$CRm) => (t2MCRR2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt,…
20474 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRm
20526 …CRm, (imm:{ *:[i32] }):$opc2) => (CDP (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:…
20532 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // CRm
[all …]
DARMGenMCCodeEmitter.inc4335 // op: CRm
4524 // op: CRm
4654 // op: CRm
4674 // op: CRm
8421 // op: CRm
10346 // op: CRm
10549 // op: CRm
10709 // op: CRm
10785 // op: CRm
10812 // op: CRm
DARMGenDAGISel.inc10033 /* 21357*/ OPC_RecordChild6, // #5 = $CRm
10054 …:$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):…
10055 …:$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):…
10069 …:$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):…
10070 …:$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):…
10090 /* 21469*/ OPC_RecordChild6, // #5 = $CRm
10109 …:$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):…
10110 …:$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):…
10124 …:$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):…
10125 …:$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):…
[all …]
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc8878 // (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
8889 // (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0)
8933 // (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
8944 // (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0)
10906 // (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
10917 // (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
10937 // (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
10948 // (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
DARMDisassembler.c5095 unsigned CRm = fieldFromInstruction_4(Val, 0, 4); in DecodeMRRC2() local
5113 MCOperand_CreateImm0(Inst, CRm); in DecodeMRRC2()
/external/v8/src/arm64/
Dconstants-arm64.h247 V_(CRm, 11, 8, Bits) \
/external/vixl/src/aarch64/
Dconstants-aarch64.h140 V_(CRm, 11, 8, ExtractBits) \
Dassembler-aarch64.cc1757 Emit(SYS | ImmSysOp1(op1) | CRn(crn) | CRm(crm) | ImmSysOp2(op2) | Rt(xt)); in sys()
2509 void Assembler::clrex(int imm4) { Emit(CLREX | CRm(imm4)); } in clrex()
/external/clang/lib/CodeGen/
DCGBuiltin.cpp4038 Value *CRm = EmitScalarExpr(E->getArg(3)); in EmitARMBuiltinExpr() local
4045 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()
4064 Value *CRm = EmitScalarExpr(E->getArg(2)); in EmitARMBuiltinExpr() local
4065 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm}); in EmitARMBuiltinExpr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp5296 unsigned CRm = fieldFromInstruction(Val, 0, 4); in DecoderForMRRC2AndMCRR2() local
5332 Inst.addOperand(MCOperand::createImm(CRm)); in DecoderForMRRC2AndMCRR2()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp5273 unsigned CRm = fieldFromInstruction(Val, 0, 4); in DecoderForMRRC2AndMCRR2() local
5309 Inst.addOperand(MCOperand::createImm(CRm)); in DecoderForMRRC2AndMCRR2()

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