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Searched refs:CTLZ (Results 1 – 25 of 108) sorted by relevance

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/external/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll8 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
28 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTLZ]]
48 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTLZ]]
128 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
129 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTLZ]]
147 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
148 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTLZ]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll8 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
28 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTLZ]]
48 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTLZ]]
128 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
129 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTLZ]]
147 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
148 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTLZ]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll9 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
10 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTLZ]]
28 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTLZ]]
48 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTLZ]]
177 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
178 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTLZ]] to i64
200 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
201 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i32
[all …]
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll9 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
10 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTLZ]]
28 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTLZ]]
48 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTLZ]]
177 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
178 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTLZ]] to i64
200 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
201 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i32
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dctlz.ll21 ; SI-DAG: s_flbit_i32_b32 [[CTLZ:s[0-9]+]], [[VAL]]
23 ; SI-DAG: v_mov_b32_e32 [[VCTLZ:v[0-9]+]], [[CTLZ]]
38 ; SI-DAG: v_ffbh_u32_e32 [[CTLZ:v[0-9]+]], [[VAL]]
39 ; SI-DAG: v_cmp_eq_i32_e32 vcc, 0, [[CTLZ]]
40 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], [[CTLZ]], 32, vcc
102 ; SI-DAG: v_cmp_eq_i32_e32 vcc, 0, [[CTLZ]]
121 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
123 ; SI: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
145 ; SI-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[ADD]], [[CMPHI]]
148 ; SI-DAG: v_cndmask_b32_e64 v[[CLTZ_LO:[0-9]+]], v[[CTLZ:[0-9]+]], 64, vcc
Dctlz_zero_undef.ll101 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
103 ; SI: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
124 ; SI-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]]
126 ; SI: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
/external/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll8 ; CHECK-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
28 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopIdiom/ARM/
Dctlz.ll4 ; Recognize CTLZ builtin pattern.
6 ; so do not insert builtin if CPU do not support CTLZ
68 ; Recognize CTLZ builtin pattern.
118 ; Recognize CTLZ builtin pattern.
160 ; Recognize CTLZ builtin pattern.
203 ; Recognize CTLZ builtin pattern.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1602 { ISD::CTLZ, MVT::v8i64, 1 }, in getIntrinsicInstrCost()
1603 { ISD::CTLZ, MVT::v16i32, 1 }, in getIntrinsicInstrCost()
1604 { ISD::CTLZ, MVT::v32i16, 8 }, in getIntrinsicInstrCost()
1605 { ISD::CTLZ, MVT::v64i8, 20 }, in getIntrinsicInstrCost()
1606 { ISD::CTLZ, MVT::v4i64, 1 }, in getIntrinsicInstrCost()
1607 { ISD::CTLZ, MVT::v8i32, 1 }, in getIntrinsicInstrCost()
1608 { ISD::CTLZ, MVT::v16i16, 4 }, in getIntrinsicInstrCost()
1609 { ISD::CTLZ, MVT::v32i8, 10 }, in getIntrinsicInstrCost()
1610 { ISD::CTLZ, MVT::v2i64, 1 }, in getIntrinsicInstrCost()
1611 { ISD::CTLZ, MVT::v4i32, 1 }, in getIntrinsicInstrCost()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dfls.ll33 ; CHECK-NEXT: [[CTLZ:%.*]] = call i64 @llvm.ctlz.i64(i64 %z, i1 false), !range !0
34 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[CTLZ]] to i32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dctlz.ll21 ; GCN-DAG: s_flbit_i32_b32 [[CTLZ:s[0-9]+]], [[VAL]]
23 ; GCN-DAG: v_mov_b32_e32 [[VCTLZ:v[0-9]+]], [[CTLZ]]
38 ; GCN: v_ffbh_u32_e32 [[CTLZ:v[0-9]+]], [[VAL]]
40 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], 32, [[CTLZ]], vcc
133 ; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
135 ; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
156 ; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[ADD]], vcc
159 ; GCN-DAG: v_cndmask_b32_e32 v[[CLTZ_LO:[0-9]+]], 64, v[[CTLZ:[0-9]+]], vcc
Dctlz_zero_undef.ll108 ; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
110 ; GCN: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
131 ; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]]
132 ; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI:[0-9]+]]{{\]}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopIdiom/X86/
Dctlz.ll4 ; Recognize CTLZ builtin pattern.
6 ; so do not insert builtin if CPU do not support CTLZ
68 ; Recognize CTLZ builtin pattern.
118 ; Recognize CTLZ builtin pattern.
164 ; Recognize CTLZ builtin pattern.
206 ; Recognize CTLZ builtin pattern.
244 ; Recognize CTLZ builtin pattern.
287 ; Recognize CTLZ builtin pattern.
326 ; Recognize CTLZ builtin pattern.
371 ; Recognize CTLZ builtin pattern.
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Dnon-vectorizable-intrinsic.ll6 ; CTLZ cannot be vectorized currently because the second argument is a scalar
9 ; Test causes an assert if LLVM tries to vectorize CTLZ.
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dnon-vectorizable-intrinsic.ll6 ; CTLZ cannot be vectorized currently because the second argument is a scalar
9 ; Test causes an assert if LLVM tries to vectorize CTLZ.
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll8 ; CHECK-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
/external/llvm/lib/Transforms/Utils/
DIntegerDivision.cpp183 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local
255 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode()
256 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Utils/
DIntegerDivision.cpp183 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local
255 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode()
256 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h320 BSWAP, CTTZ, CTLZ, CTPOP, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/
DLoopIdiomRecognize.cpp1567 Value *CTLZ, *Count, *CountPrev, *NewCount, *InitXNext; in transformLoopToCountable() local
1580 CTLZ = createCTLZIntrinsic(Builder, InitXNext, DL, ZeroCheck); in transformLoopToCountable()
1582 ConstantInt::get(CTLZ->getType(), in transformLoopToCountable()
1583 CTLZ->getType()->getIntegerBitWidth()), in transformLoopToCountable()
1584 CTLZ); in transformLoopToCountable()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h342 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h385 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp345 case ISD::CTLZ: in LegalizeOp()
733 case ISD::CTLZ: in Expand()
1095 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) { in ExpandCTLZ()
1097 return DAG.getNode(ISD::CTLZ, DL, Op.getValueType(), Op.getOperand(0)); in ExpandCTLZ()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp74 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in BlackfinTargetLowering()
113 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in BlackfinTargetLowering()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp160 case ISD::CTLZ: in LegalizeOp()

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