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Searched refs:CVT_D_W (Results 1 – 10 of 10) sorted by relevance

/external/v8/src/compiler/mips/
Dinstruction-scheduler-mips.cc345 CVT_D_W = 4, enumerator
682 Mthc1Latency() + Latency::CVT_D_W + Latency::BRANCH + in CvtDUwLatency()
683 Latency::ADD_D + Latency::CVT_D_W; in CvtDUwLatency()
1713 return Latency::CVT_D_W; in GetInstructionLatency()
/external/v8/src/compiler/mips64/
Dinstruction-scheduler-mips64.cc378 CVT_D_W = 4, enumerator
1488 return Latency::MTC1 + Latency::CVT_D_W; in GetInstructionLatency()
/external/v8/src/mips/
Dconstants-mips.h666 CVT_D_W = ((4U << 3) + 1), enumerator
Ddisasm-mips.cc1246 case CVT_D_W: // Convert word to double. in DecodeTypeRegisterWRsType()
Dassembler-mips.cc3129 GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W); in cvt_d_w()
Dsimulator-mips.cc3074 case CVT_D_W: // Convert word to double. in DecodeTypeRegisterWRsType()
/external/v8/src/mips64/
Dconstants-mips64.h696 CVT_D_W = ((4U << 3) + 1), enumerator
Ddisasm-mips64.cc1319 case CVT_D_W: // Convert word to double. in DecodeTypeRegisterWRsType()
Dassembler-mips64.cc3446 GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W); in cvt_d_w()
Dsimulator-mips64.cc3367 case CVT_D_W: // Convert word to double. in DecodeTypeRegisterWRsType()