| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRISelDAGToDAG.cpp | 271 SDValue CopyToReg = in SelectInlineAsmMemoryOperand() local
275 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL)); in SelectInlineAsmMemoryOperand()
300 SDValue CopyToReg = CurDAG->getCopyToReg(Op, dl, VReg, Op); in SelectInlineAsmMemoryOperand() local
302 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL)); in SelectInlineAsmMemoryOperand()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 114 if (User->getOpcode() == ISD::CopyToReg && in EmitCopyFromReg()
197 if (User->getOpcode() == ISD::CopyToReg && in getDstOfOnlyCopyToRegUse()
246 if (User->getOpcode() == ISD::CopyToReg && in CreateVirtualRegisters()
479 if (User->getOpcode() == ISD::CopyToReg && in EmitSubregNode()
853 } else if (F->getOpcode() == ISD::CopyToReg) { in EmitMachineNode()
897 case ISD::CopyToReg: { in EmitSpecialNode()
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| D | ResourcePriorityQueue.cpp | 89 case ISD::CopyToReg: break; in numberRCValPredInSU()
126 case ISD::CopyToReg: NumberDeps++; break; in numberRCValSuccInSU()
457 case ISD::CopyToReg: in SUSchedulingCost()
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| D | ScheduleDAGSDNodes.cpp | 114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) in CheckForPhysRegDependency()
409 if (SUNode->getOpcode() != ISD::CopyToReg) in BuildSchedUnits()
639 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in computeOperandLatency()
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| D | ScheduleDAGRRList.cpp | 681 case ISD::CopyToReg: in EmitNode()
1890 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in getNodePriority()
2107 if (N->getOpcode() != ISD::CopyToReg) in unscheduledNode()
2193 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) in closestSucc()
2241 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { in hasOnlyLiveOutUses()
2570 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in canEnableCoalescing()
2811 if (N->getOpcode() == ISD::CopyToReg && in PrescheduleNodesWithMultipleUses()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 86 case ISD::CopyToReg: break; in numberRCValPredInSU()
122 case ISD::CopyToReg: NumberDeps++; break; in numberRCValSuccInSU()
444 case ISD::CopyToReg: in SUSchedulingCost()
|
| D | InstrEmitter.cpp | 114 if (User->getOpcode() == ISD::CopyToReg && in EmitCopyFromReg()
198 if (User->getOpcode() == ISD::CopyToReg && in getDstOfOnlyCopyToRegUse()
246 if (User->getOpcode() == ISD::CopyToReg && in CreateVirtualRegisters()
502 if (User->getOpcode() == ISD::CopyToReg && in EmitSubregNode()
933 } else if (F->getOpcode() == ISD::CopyToReg) { in EmitMachineNode()
977 case ISD::CopyToReg: { in EmitSpecialNode()
|
| D | ScheduleDAGSDNodes.cpp | 115 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) in CheckForPhysRegDependency()
410 if (SUNode->getOpcode() != ISD::CopyToReg) in BuildSchedUnits()
640 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in computeOperandLatency()
|
| D | ScheduleDAGRRList.cpp | 705 case ISD::CopyToReg: in EmitNode()
2016 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in getNodePriority()
2232 if (N->getOpcode() != ISD::CopyToReg) in unscheduledNode()
2318 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) in closestSucc()
2366 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { in hasOnlyLiveOutUses()
2695 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in canEnableCoalescing()
2937 if (N->getOpcode() == ISD::CopyToReg && in PrescheduleNodesWithMultipleUses()
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | copy-to-reg.ll | 4 ; Test that CopyToReg instructions don't have non-register operands prior
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | copy-to-reg.ll | 4 ; Test that CopyToReg instructions don't have non-register operands prior
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 376 if (UI->getOpcode() == ISD::CopyToReg) { in SelectAddrRI12()
425 if (UI->getOpcode() == ISD::CopyToReg) { in SelectAddrRI()
468 if (UI->getOpcode() == ISD::CopyToReg) { in SelectAddrRRI12()
517 if (UI->getOpcode() == ISD::CopyToReg) { in SelectAddrRRI20()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 96 if (User->getOpcode() == ISD::CopyToReg && in EmitCopyFromReg()
177 if (User->getOpcode() == ISD::CopyToReg && in getDstOfOnlyCopyToRegUse()
212 if (User->getOpcode() == ISD::CopyToReg && in CreateVirtualRegisters()
437 if (User->getOpcode() == ISD::CopyToReg && in EmitSubregNode()
804 case ISD::CopyToReg: { in EmitSpecialNode()
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| D | ScheduleDAGSDNodes.cpp | 106 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) in CheckForPhysRegDependency()
371 if (SUNode->getOpcode() != ISD::CopyToReg) in BuildSchedUnits()
592 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in ComputeOperandLatency()
|
| D | ScheduleDAGRRList.cpp | 560 case ISD::CopyToReg: in EmitNode()
1781 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in getNodePriority()
1999 if (N->getOpcode() != ISD::CopyToReg) in UnscheduledNode()
2087 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) in closestSucc()
2138 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { in hasOnlyLiveOutUses()
2495 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in canEnableCoalescing()
2737 if (N->getOpcode() == ISD::CopyToReg && in PrescheduleNodesWithMultipleUses()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 160 CopyToReg, enumerator
|
| D | SelectionDAG.h | 400 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
411 return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);
419 return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 165 CopyToReg, enumerator
|
| D | SelectionDAG.h | 584 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
595 return getNode(ISD::CopyToReg, dl, VTs,
604 return getNode(ISD::CopyToReg, dl, VTs,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 170 CopyToReg, enumerator
|
| D | SelectionDAG.h | 676 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
687 return getNode(ISD::CopyToReg, dl, VTs,
696 return getNode(ISD::CopyToReg, dl, VTs,
|
| /external/llvm/test/CodeGen/WebAssembly/ |
| D | userstack.ll | 192 ; The use of the alloca in a phi causes a CopyToReg DAG node to be generated,
193 ; which has to have special handling because CopyToReg can't have a FI operand
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 116 setOperationAction(ISD::CopyToReg, MVT::Other, Custom); in WebAssemblyTargetLowering()
554 case ISD::CopyToReg: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/WebAssembly/ |
| D | userstack.ll | 271 ; The use of the alloca in a phi causes a CopyToReg DAG node to be generated,
272 ; which has to have special handling because CopyToReg can't have a FI operand
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 131 setOperationAction(ISD::CopyToReg, MVT::Other, Custom); in WebAssemblyTargetLowering()
751 case ISD::CopyToReg: in LowerOperation()
|