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Searched refs:DIV64 (Results 1 – 6 of 6) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dslow-div.ll2 …llc -mtriple=x86_64-unknown-linux-gnu -mattr=+idivq-to-divw < %s | FileCheck -check-prefix=DIV64 %s
10 ; DIV64-LABEL: div32:
11 ; DIV64-NOT: divb
20 ; DIV64-LABEL: div64:
21 ; DIV64: orq %{{.*}}, [[REG:%[a-z]+]]
22 ; DIV64: testq $-65536, [[REG]]
23 ; DIV64: divw
Dcrash-O0.ll33 ; When using fast isel, sdiv is lowered into a sequence of CQO + DIV64.
34 ; CQO defines implicitly AX and DIV64 uses it implicitly too.
38 ; An instruction gets between CQO and DIV64 because the load is folded
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dcrash-O0.ll33 ; When using fast isel, sdiv is lowered into a sequence of CQO + DIV64.
34 ; CQO defines implicitly AX and DIV64 uses it implicitly too.
38 ; An instruction gets between CQO and DIV64 because the load is folded
/external/mesa3d/src/compiler/glsl/
Dir_optimization.h61 #define DIV64 (1U << 2) macro
Dlower_int64.cpp363 if (lowering(DIV64)) { in handle_rvalue()
/external/mesa3d/src/mesa/state_tracker/
Dst_glsl_to_tgsi.cpp6967 lower_64bit_integer_instructions(ir, DIV64 | MOD64); in st_link_shader()