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Searched refs:DPCD_TRAINING_LANE0_SET (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/video/exynos/
Dexynos_dp.c582 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); in exynos_dp_process_clock_recovery()
681 DPCD_TRAINING_LANE0_SET, in exynos_dp_process_equalizer_training()
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dedp_rk3288.h468 #define DPCD_TRAINING_LANE0_SET (0x0103) macro
/external/u-boot/arch/arm/mach-exynos/include/mach/
Ddp.h623 #define DPCD_TRAINING_LANE0_SET (0x0103) macro
/external/u-boot/drivers/video/rockchip/
Drk_edp.c482 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET, in rk_edp_link_train_cr()