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Searched refs:DefaultMode (Results 1 – 12 of 12) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DInfoByHwMode.h37 DefaultMode = CodeGenHwModes::DefaultMode, enumerator
50 bool HasDefault = U.count(DefaultMode); in union_modes()
52 if (M != DefaultMode) in union_modes()
55 V.push_back(DefaultMode); in union_modes()
83 bool hasDefault() const { return hasMode(DefaultMode); } in hasDefault()
87 assert(hasMode(DefaultMode)); in get()
88 Map.insert({Mode, Map.at(DefaultMode)}); in get()
94 if (Mode != DefaultMode && F == Map.end()) in get()
95 F = Map.find(DefaultMode); in get()
102 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isSimple()
[all …]
DRegisterBankEmitter.cpp88 else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize < in addRegisterClass()
89 RC->RSI.get(DefaultMode).SpillSize) in addRegisterClass()
247 unsigned Size = RC.RSI.get(DefaultMode).SpillSize; in emitBaseClassImplementation()
DInfoByHwMode.cpp28 if (Mode == DefaultMode) in getModeName()
65 auto D = Map.find(DefaultMode); in getOrCreateTypeForMode()
DCodeGenHwModes.h43 enum : unsigned { DefaultMode = 0 }; enumerator
DCodeGenHwModes.cpp82 return DefaultMode; in getHwModeId()
DCodeGenDAGPatterns.cpp112 if (Modes.count(DefaultMode)) { in insert()
113 MVT DT = VVT.getType(DefaultMode); in insert()
127 if (M == DefaultMode || hasMode(M)) in constrain()
129 Map.insert({M, Map.at(DefaultMode)}); in constrain()
805 VTS.getOrCreate(DefaultMode) = LegalCache; in getLegalTypes()
1595 if (S.get(DefaultMode).empty()) in setDefaultMode()
4157 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4171 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4176 bool HasDefault = Modes.count(DefaultMode); in ExpandHwModeBasedTypes()
4178 AppendPattern(P, DefaultMode); in ExpandHwModeBasedTypes()
DCodeGenDAGPatterns.h225 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isDefaultOnly()
DCodeGenRegisters.cpp792 RSI.Map.insert({DefaultMode, RI}); in CodeGenRegisterClass()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td273 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
275 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
277 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
279 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
282 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
284 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
286 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
289 def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
291 def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
293 def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td87 def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
101 [RV32, RV64, DefaultMode],
116 [RV32, RV64, DefaultMode],
129 [RV32, RV64, DefaultMode],
138 [RV32, RV64, DefaultMode],
151 [RV32, RV64, DefaultMode],
157 [RV32, RV64, DefaultMode],
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DHwModeSelect.td24 def BadDef : ValueTypeByHwMode<[TestMode1, TestMode2, DefaultMode],
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTarget.td37 def DefaultMode : HwMode<"">;